Digital to analog converter with reduced ringing
View Patent ↗Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.
1. A digital-to-analog converter (DAC), comprising:
a first circuit configured to decode a digital signal to provide a first output according to a clock signal, the first circuit latching the first output after the digital signal has settled; and
a second circuit configured to provide a second output representative of an analog value of the digital signal based on the first output.
2. The DAC of claim 1 , wherein the digital signal represents one or more binary indications indicative of a thermometer code.
3. The DAC of claim 2 , wherein the analog value represents an analog representation of at least one of the binary indications.
4. The DAC of claim 1 , wherein the first circuit comprises:
a decoder configured to decode the digital signal to provide a decoded output representative of the digital signal; and
a latch configured to latch the decoded output to provide the first output.
5. The DAC of claim 4 , wherein the digital signal represents one or more binary indications indicative of a thermometer code.
6. The DAC of claim 5 , wherein the decoder decodes the binary indications corresponding to at least one cell in a matrix.
7. The DAC of claim 1 , wherein the first circuit is configured to provide the first output in synchronism with the clock signal after the digital signal has settled.
8. The DAC of claim 1 , wherein the first circuit is configured to provide the first output after the digital signal has settled to a steady state value.
9. The DAC of claim 1 , wherein the second circuit comprises:
a current source including only transistors of a p-type to provide the second value.
10. The DAC of claim 1 , wherein the first circuit and the second circuit are implemented in CMOS.
11. A method to convert a digital signal to an analog value, comprising:
(a) decoding a digital signal to provide a first output according to a clock signal;
(b) latching the first output after the digital signal has settled; and
(c) providing a second output representative of the analog value of the digital signal based on the first output.
12. The method of claim 11 , wherein step (a) comprises:
(a)(i) decoding one or more binary indications indicative of a thermometer code to provide the first output.
13. The method of claim 12 , wherein step (c) comprises:
(c)(i) providing the second output representative of an analog representation of the one or more binary indications based on the first output.
14. The method of claim 12 , wherein step (a) comprises:
(a)(i) decoding the one or more binary indications corresponding to at least one cell in a matrix.
15. The method of claim 11 , wherein step (b) comprises:
(b)(i) latching the first output in synchronism with the clock signal after the digital signal has settled.
16. The method of claim 11 , wherein step (b) comprises:
(b)(i) latching the first output after the digital signal has settled to a steady state value.
17. The method of claim 11 , wherein step (c) comprises:
(c)(i) providing a current representative of the analog value of the digital signal based on the first output.
18. The method of claim 17 , wherein step (c)(i) comprises:
(c)(i)(A) providing the current using only transistors of a p-type.