Timing functions to optimize code-execution time
View Patent ↗A method and system for optimizing a test plan of an Integrated Circuit (IC). The test plan includes two or more test sequences. A test sequence includes the measurement of a parameter of the IC. The total test time of the IC is reduced by performing one or more activities during a desired wait time associated with the measurement of the parameter. The test plan may be further optimized by modifying the one or more activities performed during the desired wait time.
1. A method for executing a test sequence for testing an integrated circuit, the test sequence comprising measurement of at least one parameter of the integrated circuit, the method comprising:
a) initializing the measurement of the at least one parameter, the measurement having a desired wait time;
b) performing one or more activities during the desired wait time;
c) performing the measurement of the at least one parameter at the end of the desired wait time; and
d) modifying the test sequence based on at least one of the desired wait time, and the difference between the desired wait time and the time elapsed in performing the one or more activities.
2. The method according to claim 1 , wherein modifying the test sequence includes inserting one or more other activities in the test sequence.
3. The method according to claim 1 , wherein modifying the test sequence includes removing at least one of the one or more activities from the test sequence.
4. The method according to claim 1 , wherein modifying the test sequence includes modifying one or more attributes of at least one of the one or more activities performed during the desired wait time.
5. The method according to claim 1 , wherein the one or more activities comprises at least one of measuring one or more other parameters of the integrated circuit, transferring data between at least two of the integrated circuit, a measurement instrument and a host computer, processing the data on the host computer, configuring the measurement instrument, executing another test sequence and introducing a delay having a time period equal to the desired wait time.
6. The method according to claim 1 , wherein the method is implemented as a computer readable program code comprising a set of instructions for executing a test sequence for testing an integrated circuit embodied in a computer usable medium, wherein the set of instructions are executed by a microprocessor.
7. The method according to claim 1 further comprising logging at least one of the desired wait time, the time elapsed in performing the one or more activities, and the difference between the desired wait time and the time elapsed in performing the one or more activities.
8. The method according to claim 1 further comprising modifying the measurement of the at least one parameter based on the desired wait time, and the difference between the desired wait time and the time elapsed in performing the one or more activities.