High-voltage lateral DMOS device with diode clamp
View Patent ↗All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
1. A lateral DMOS device formed in a semiconductor substrate of a first conductivity type, the substrate not comprising an epitaxial layer, the device comprising:
a source region of the second conductivity type formed adjacent the surface of the substrate;
a drain region of the second conductivity type located adjacent the surface of the substrate, the drain region being spaced apart from the source region;
a drift region of a second conductivity type located adjacent the surface of the substrate and the drain region, the drift region being spaced apart from the source region, a channel region of the first conductivity type being located between the drift region and the source region;
a gate dielectric layer and a gate overlying the channel region; and
a diode clamp comprising a deep region of the first conductivity type, the deep region having a doping concentration greater than a doping concentration of the substrate, the entire deep region being located directly below the drain region, a PN junction between the drain region and the deep region being completely submerged in the substrate, wherein the deep region of the first conductivity type comprises a vertical series of contiguous dopant regions having different doping concentrations, respectively, and wherein within the deep region a doping concentration of a dopant region deeper in the substrate is greater than a doping concentration of a dopant region shallower in the substrate.
2. The Lateral DMOS device of claim 1 wherein the body region comprises a vertical series of dopant regions having different doping concentrations, respectively.
3. The lateral DMOS device of claim 2 wherein within the body region a doping concentration of a dopant region deeper in the substrate is greater than a doping concentration of a dopant region shallower in the substrate.
4. The lateral DMOS device of claim 1 wherein the drift region extends to a level deeper in the substrate than the drain region.
5. The lateral DMOS device of claim 4 wherein the drift region is spaced apart from the deep region.
6. The lateral DMOS device of claim 5 wherein a portion of the drift region extends under the gate dielectric layer, the gate dielectric layer being of substantially uniform thickness.
7. The lateral DMOS device of claim 1 comprising sidewall spacers on the sides of the gate.
8. The lateral DMOS device of claim 1 wherein the diode clamp comprises a Zener diode.