IP Library Granted Patent US 7,532,071
Granted Patent B2
US 7,532,071 · App. 11/984,261 · Granted May 12, 2009

Operational amplifier circuit

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Quick Facts
Patent No.
US 7,532,071
App. No.
11/984,261
Granted
May 12, 2009
Kind
B2
Abstract

A level shifter unit outputting a level shifted signal generated by level shifting of output signals of the first and second differential amplifier circuits, and an output circuit including complementary output transistors series being coupled between the high potential power supply and the low potential power supply and inputting the level shifted signal.

Claims (21)

1. An operational amplifier circuit, comprising:

first and second differential amplifier circuits, at least one of which operates in response to an input signal within a voltage range between a high potential power supply and a low potential power supply;

a level shifter unit outputting a level shifted signal generated by level shifting of output signals of the first and second differential amplifier circuits; and

an output circuit including complementary output transistors series being coupled between the high potential power supply and the low potential power supply and inputting the level shifted signal;

wherein the level shifter unit outputs the level shifted voltage as a voltage obtained by a subtraction of threshold values of the complementary output transistors from a potential difference between the high potential power supply and the low potential power supply, and wherein the level shifter unit includes a voltage regulating unit regulating the level shifted voltage so as to cancel variations in the threshold values of the complementary output transistors.

2. An operational amplifier circuit according to claim 1 , wherein:

the complementary output transistors series includes a P-channel MOS transistor and a N-channel MOS transistor;

wherein the level shifter unit includes:

a current mirror circuit including a pair of P-channel MOS transistors, each of the pair of transistors having a source coupled to the high potential power supply; and

a current mirror circuit including N-channel MOS transistors each having a source coupled to the low potential power supply;

wherein the current mirror circuits are connected together via a resistor; and

wherein a terminal-to-terminal voltage of the resistor is output as the level shifted voltage to the output circuit, and the P-channel MOS transistor and the N-channel MOS transistor of the current mirror circuits are operated to serve as the voltage regulating unit.

3. An operational amplifier circuit according to claim 1 , wherein:

the complementary output transistor series includes a PNP transistor and an NPN transistor;

wherein the level shifter unit includes:

a current mirror circuit including a pair of PNP transistors, each of the pair of transistors having an emitter coupled to the high potential power supply; and

a current mirror circuit including NPN transistors, each having an emitter coupled to the low potential power supply;

wherein the current mirror circuits are connected together via a resistor; and

wherein a terminal-to-terminal voltage of the resistor is output as the level shifted voltage to the output circuit, and the PNP transistor and the NPN transistor of the current mirror circuits are operated to serve as the voltage regulating unit.

4. An operational amplifier circuit according to claim 2 , wherein sizes of the transistors included in the output circuit and sizes of the transistors included in the current mirror circuits are set so that threshold value fluctuations due to process variations are identical to each other.

5. An operational amplifier circuit according to claim 3 , wherein sizes of the transistors included in the output circuit and sizes of the transistors included in the current mirror circuits are set so that threshold value fluctuations due to process variations are identical to each other.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036044/0745 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024982/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021977/0219 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2007
From: WILLIAMS, MARTIN; MCLEOD, MATTHEW; KOYA, KEIZO
To: SYNTA PHARMACEUTICALS CORP.
Reel/Frame 020164/0346 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2007
From: MIYATA, SHINJI
To: FUJITSU LIMITED
Reel/Frame 020162/0210 →