Semiconductor memory system and signal processing system
View Patent ↗A semiconductor memory device provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.
1. A semiconductor memory device comprising:
a cell array formed by a plurality of memory cells storing page data therein arranged in a matrix,
wherein the page data is stored in the cell array in units of pages the page data is divided into a plurality of sectors,
the plurality of sectors are divided into a plurality of code words and a plurality of check codes corresponding to the plurality of code words, and
the plurality of sectors are successively transferred to a latch circuit;
a plurality of shift registers able to successively shift and hold the plurality of code words included in the page data to be written;
a first switch circuit for receiving the page data to be written including the plurality code words and inputting at least a successive code word of the plurality of code words to the plurality of shift registers;
a second switch circuit for selectively outputting the successive code word data of each shift register in which the successive code words are all shifted;
a check code generation circuit for checking the successive code words selected so as to be output by the second switch circuit and generating the check codes; and
an additional circuit for adding the check codes to the successive code words selectively output by the second switch circuit and outputting the same as the main code words to the latch circuit.
2. A semiconductor memory device as set forth in claim 1 , wherein the page data including the plurality of sectors composed of the plurality of code words and check codes are stored in the cell array in units of pages all together.
3. A semiconductor memory device as set forth in claim 2 , wherein the units of pages are units of word lines.
4. A semiconductor memory device as set forth in claim 1 , wherein said cell array includes NAND memory strings formed by a plurality of memory cells connected in series.
5. A semiconductor memory device as set forth in claim 1 , wherein the unit of pages are units of word lines.
6. A semiconductor memory device as set forth in claim 1 , wherein the latch circuit is configured for latching the page data to be written that includes at least the plurality of sectors.
7. A semiconductor memory device as set forth in claim 1 , further comprising:
a correction circuit, positioned in parallel with the plurality of shift registers, that corrects errors in the page data when a number of errors in a given main code word is within a predetermined number of errors, adding corresponding error correction information to the given main code word, except the check code, and outputting the result; and
an additional circuit that adds the error correction information from the correction circuit to the successive code words output by the second switch circuit and outputs corrected code words.
8. A semiconductor memory device as set forth in claim 7 , wherein said data output portion further comprises a syndrome data generator, and syndrome data output, and wherein while performing error correction, the error correction circuit outputs the syndrome data when it is unable to correct an error.
9. A semiconductor memory device as set forth in claim 7 , wherein the error correction circuit of said data output portion further comprises an output for indicating the state of the error correction.