Methods and apparatuses for stacked capacitors for image sensors
Capacitive circuits and methods of forming capacitive circuits including a first capacitor and a second capacitor connected in parallel to the first capacitor, wherein the first capacitor is positioned at least partially above the second capacitor.
1 . A capacitive circuit comprising:
a first capacitor; and
a second capacitor electrically connected in parallel to the first capacitor,
wherein the first capacitor is positioned at least partially above the second capacitor.
2 . The capacitive circuit of claim 1 , wherein:
the first capacitor comprises one of: a poly-poly capacitor, a metal-insulator-metal (MIM) capacitor, and a poly-insulator-metal (PIM) capacitor; and
the second capacitor comprises one of: a poly-poly capacitor, a metal-insulator-metal (MIM) capacitor, and a poly-insulator-metal (PIM) capacitor.
3 . The capacitive circuit of claim 1 , wherein the first and second capacitors comprises the same type of capacitor materials.
4 . The capacitive circuit of claim 1 , wherein the first and second capacitors comprises different types of capacitor materials.
5 . The capacitive circuit of claim 1 , further comprising a third capacitor positioned at least partially below and electrically connected to the second capacitor.
6 . The capacitive circuit of claim 1 , wherein the capacitive circuit comprises a sample and hold circuit for an imaging device.
7 . The capacitive circuit of claim 1 , wherein:
the first capacitor comprises a first top plate, a first bottom plate, and a first dielectric material between the first top and bottom plates; and
the second capacitor comprises a second top plate, a second bottom plate, and a second dielectric material between the second top and bottom plates.
8 . The capacitive circuit of claim 7 , further comprising:
a substrate,
wherein the second capacitor is formed over the substrate.
9 . The capacitive circuit of claim 8 , wherein the substrate functions as a second bottom plate for the second capacitor.
10 . The capacitive circuit of claim 7 , wherein each of the first and second top and bottom plates comprises a polysilicon material or a metal material.
11 . The capacitive circuit of claim 10 , wherein the polysilicon material comprises a doped polysilicon material.
12 . The capacitive circuit of claim 10 , wherein the a metal material comprises one of: copper, aluminum, tungsten, and tantalum.
13 . The capacitive circuit of claim 7 , wherein the first and second dielectric materials each comprise an oxide material or a nitride material.
14 . The capacitive circuit of claim 13 , wherein the oxide material comprises hafnium oxide or tantalum tin oxide.
15 . The capacitive circuit of claim 7 , further comprising:
first and second metal connectors for electrically connecting the first and second capacitors in parallel.
16 . The capacitive circuit of claim 15 , further comprising a via for electrically connecting first and second portions of the first metal connector,
wherein the first bottom plate of the first capacitor comprises a metal material.
17 . A capacitive circuit comprising:
a first capacitor; and
a second capacitor stacked over and electrically connected in parallel to the first capacitor.
18 . An imaging device comprising:
a readout circuit, the readout circuit comprising:
a sample and hold circuit, the sample and hold circuit comprising:
the capacitive circuit of claim 17 .
19 . A camera comprising:
an imager, the imager comprising:
a sample and hold circuit, the sample and hold circuit comprising:
the capacitive circuit of claim 17 .
20 . A method of forming a capacitive circuit comprising:
forming a lower capacitor over a semiconductor substrate;
forming an upper capacitor positioned at least partially over the lower capacitor, the upper capacitor electrically connected in parallel to the lower capacitor.
21 . The method of claim 20 , wherein forming the upper capacitor comprises:
forming a first bottom plate over the lower capacitor;
forming a first dielectric layer over the first bottom plate; and
forming a first top plate over the first dielectric layer.
22 . The method of claim 21 , wherein forming the lower capacitor comprises:
forming a second dielectric layer over the substrate; and
forming a second top plate over the second dielectric layer.
23 . The method of claim 22 , wherein forming the lower capacitor further comprises:
forming a second bottom plate below the second dielectric layer; and
forming an oxide layer between the second bottom plate and the substrate.
24 . The method of claim 20 , further comprising:
forming first and second metal connectors for electrically connecting the first and second capacitors in parallel.
25 . The method of claim 20 , wherein forming the upper capacitor comprises:
forming a via in a metal layer;
coating an interior surface of the via with an dielectric material; and
filling the via with a metal material.