DSL trellis encoding
View Patent ↗A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.
1. A method for trellis encoding data for subsequent modulation onto one or more pairs of tones, the method comprising:
receiving a first operand including state input bits for a first trellis stage;
receiving a second operand including data input bits for a plurality of trellis stages, the plurality of trellis stages including the first trellis stage and a final trellis stage; and
generating a trellis encoded output for subsequent modulation onto the one or more pairs of tones based on the first operand, the second operand, and data output bits,
wherein the trellis encoded output comprises state output bits from the final trellis stage,
wherein the data output bits include a plurality of sets of data output bits from the plurality of trellis stages, and
wherein the plurality of sets of data output bits from the plurality of trellis stages are generated substantially simultaneously.
2. The method of claim 1 , wherein the step of generating the trellis encoded output for subsequent modulation onto the one or more pairs of tones comprises:
modulating the trellis encoded output for subsequent modulation onto two pairs of tones.
3. The method of claim 2 , wherein the step of generating the trellis encoded output comprises:
generating a first 64-bit value for a first set of data output bits and a second 64-bit value for a second set of data output bits.
4. The method of claim 2 , wherein the step of generating the trellis encoded output comprises:
generating state bits S(2) for the state output bits.
5. The method of claim 2 , wherein the step of generating the trellis encoded output comprises:
generating data output bits V(1), W(1) for a first set of data output bits and data output bits V(2), W(2) for a second set of data output bits.
6. The method of claim 2 , wherein the step of receiving the first operand comprises:
receiving a 64-bit value for the first operand.
7. The method of claim 6 , wherein the step of receiving the 64-bit value for the first operand comprises:
receiving the 64-bit value including a 4-bit value for the state input bits for the first operand.
8. The method of claim 2 , wherein the step of receiving the second operand comprises:
receiving a 64-bit value for the second operand.
9. The method of claim 8 , wherein the step of receiving the 64-bit value for the second operand comprises:
receiving a first field of 32-bits and a second field of 32-bits for the second operand.
10. The method of claim 9 , wherein the step of receiving the first field of 32-bits and the second field of 32-bits for the second operand comprises:
receiving U(0) bits for the first field and U(1) bits for the second field.
11. An instruction mechanism to trellis encode data for subsequent modulation onto one or more pairs of tones, comprising:
an instruction decoder configured to receive a single instruction; and
an execution unit configured to trellis encode data for subsequent modulation onto the one or more pairs of tones in response to the single instruction, the trellis encoding including:
receiving a first operand including state input bits for a first trellis stage,
receiving a second operand including data input bits for a plurality of trellis stages, the plurality of trellis stages including the first trellis stage and a final trellis stage, and
generating a trellis encoded output for subsequent modulation onto the one or more pairs of tones based on the first operand, the second operand, and data output bits,
wherein the trellis encoded output includes state output bits from the final trellis stage,
wherein the data output bits include a plurality of sets of data output bits from the plurality of trellis stages, and
wherein the plurality of sets of data output bits from the plurality of trellis stages are generated substantially simultaneously.
12. The instruction mechanism of claim 11 , wherein the execution unit is configured to generate the trellis encoded output for subsequent modulation onto two pairs of tones.
13. The instruction mechanism of claim 12 , wherein a first set of data output bits comprises a first 64-bit value and a second set of data output bits comprises a second 64-bit value.
14. The instruction mechanism of claim 12 , wherein the state output bits comprises state bits S(2).
15. The instruction mechanism of claim 12 , wherein a first set of data output bits comprises data output bits V(1), W(1) and a second set of data output bits comprises data output bits V(2), W(2).
16. The instruction mechanism of claim 12 , wherein the execution unit comprises:
an encoding unit configured to trellis encode the data,
wherein the trellis encoding unit is configured to generate the trellis encoded output for subsequent modulation onto the one or more pairs of tones.
17. The instruction mechanism of claim 12 , wherein the first operand comprises a 64-bit value.
18. The instruction mechanism of claim 17 , wherein the 64-bit value comprises a 4-bit value for the state input bits for the first operand.
19. The instruction mechanism of claim 12 , wherein the second operand comprises a 64-bit value.
20. The instruction mechanism of claim 19 , wherein the 64-bit value comprises a first field of 32-bits and a second field of 32-bits for the second operand.
21. The instruction mechanism of claim 20 , wherein the first field of 32-bits comprises U(0) bits and the second field of 32-bits comprises U(1) bits.