Semiconductor integrated circuit including charging pump
View Patent ↗In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN 1 and MP 1 ) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.
1. A semiconductor device comprising:
a voltage generator receiving a first voltage and generating a second voltage on an output node, the second voltage being different from the first voltage,
wherein the voltage generator includes a first charge pump circuit that has a first capacitor receiving a first clock to a first node of the first capacitor, a first PMOS transistor of which source and drain are connected between a second node of the first capacitor and the output node of the voltage generator, and a first NMOS transistor of which source and drain are connected between the second node of the first capacitor and the output node of the voltage generator,
wherein the voltage generator further includes a second charge pump circuit that has a second capacitor receiving a second clock to a first node to the second capacitor, a third PMOS transistor of which source and drain are connected between a second node of the second capacitor and the output node of the voltage generator, a third NMOS transistor of which source and drain are connected between the second node of the second capacitor and the output node of the voltage generator,
wherein the second clock is an inversion clock of the first clock,
wherein a gate of the first PMOS transistor is connected to the second node of the first capacitor,
wherein a gate of the third PMOS transistor is connected to the second node of the second capacitor,
wherein a gate of the first NMOS transistor is connected to the second node of the second capacitor,
wherein a gate of the third NMOS transistor is connected to the second node of the first capacitor.
2. A semiconductor device according to claim 1 , further comprising:
a logic circuit block including a second PMOS transistor,
wherein a substrate bias of the first PMOS transistor is electrically separated from the substrate bias of the second PMOS transistor.
3. A semiconductor device according to claim 2 ,
wherein the logic circuit block includes a second NMOS transistor,
wherein the first PMOS transistor includes a first n-well formed on a first deep n-well and the first NMOS transistor includes a first p-well formed on the first deep n-well,
wherein the second PMOS transistor includes a second n-well formed on a second deep n-well and the second NMOS transistor includes a second p-well formed on the second deep n-well, and
wherein the first deep n-well is electrically separated from the second deep n-well.
4. A semiconductor device according to claim 3 , further comprising:
a guard band provided between the first deep n-well and the second deep n-well and supplied with a fixed potential.
5. A semiconductor device according to claim 3 ,
wherein the second voltage generated by the voltage generator is supplied to the second n-well.