Transistor and method of manufacturing the same

1. A method of manufacturing a transistor, comprising the steps of:

forming a vertical channel layer on a first substrate;

sequentially forming a gate insulating layer and a gate electrode on a surface of the vertical channel layer so as to form a vertical structure comprising the vertical channel layer, the gate insulating layer, and the gate electrode;

separating the vertical structure from the first substrate;

laying the vertical structure lengthwise on a second substrate forming a mask layer exposing both ends of the vertical structure on the second substrate;

sequentially removing portions of the gate electrode and the gate insulating layer from both ends of the exposed vertical structure; and

forming a source electrode and a drain electrode contacting respective ends of the vertical structure.

2. The method of claim 1 , wherein the first substrate is a semiconductor substrate having a single crystal structure.

3. The method of claim 1 , wherein the vertical channel layer is formed by etching the first substrate.

4. The method of claim 1 , wherein the vertical channel layer is formed using a single crystal growth method.

5. The method of claim 1 , wherein the vertical channel layer is one of a carbon nano tube (CNT) layer, a Si layer, a ZnO layer, a GaN layer, a GaP layer, and an InP layer.

6. The method of claim 1 , wherein the channel layer is one of cylindrical, hexagonal, and planar in shape.

7. The method of claim 1 , wherein a plurality of vertical layers identical to the vertical layer are formed, and the gate insulating layer and the gate electrode sequentially surround the vertical channel layers.

8. The method of claim 1 , further comprising the step of reducing one of a diameter and a thickness of the vertical channel layer before forming the gate insulating layer.

9. The method of claim 8 , wherein the step of reducing one of a diameter and a thickness of the vertical channel layer comprises:

forming an oxide layer by oxidizing a surface of the vertical channel layer; and

removing the oxide layer.

10. The method of claim 1 , wherein the gate insulating layer is formed of one of SiO x , Si x ,N y , and a material having a greater dielectric constant than Si x N y .

11. The method of claim 1 , wherein the second substrate is one of a glass substrate, a plastic substrate, and a semiconductor substrate.

12. The method of claim 1 , wherein a plurality of vertical structures identical to the vertical structure are laid on the second substrate.

13. The method of claim 12 , wherein the vertical structures are arranged on the second substrate in one of a single-layer structure and a multi-layer structure.

14. The method of claim 1 , wherein, when removing the gate electrode from both ends of the vertical structure, a portion of the gate electrode under the mask layer is under-cut.

15. The method of claim 1 , wherein the step of forming a source electrode and a drain electrode comprises:

forming a source/drain electrode layer on the second substrate and the mask layer so as to cover both ends of the vertical structure; and

removing the mask layer and the source/drain electrode layer on the mask layer.

16. The method of claim 1 , wherein the step of forming a source electrode and a drain electrode comprises:

forming a source/drain electrode layer on the second substrate and the mask layer so as to cover both ends of the vertical structure;

polishing the source/drain electrode layer until the mask layer is exposed; and

removing the mask layer.

17. The method of claim 1 , wherein a contact electrode contacting the gate electrode is further formed on the second substrate.

18. The method of claim 17 , wherein the contact electrode is formed on the gate electrode.

19. The method of claim 17 , wherein the contact electrode is formed under the gate electrode.