Thin film transistor, method of fabricating the same, and display device including the same

1 . A thin film transistor (TFT), comprising:

a substrate;

a semiconductor layer on the substrate;

a thermal oxide layer on the semiconductor layer;

a gate electrode on the thermal oxide layer, the gate electrode positioned to correspond to a channel region of the semiconductor layer;

an interlayer insulating layer on the substrate; and

source and drain electrodes electrically connected to the semiconductor layer.

2 . The TFT as claimed in claim 1 , wherein the thermal oxide layer includes silicon oxide.

3 . The TFT as claimed in claim 1 , wherein the thermal oxide layer has a thickness of about 50 angstroms to about 300 angstroms.

4 . The TFT as claimed in claim 3 , wherein the thermal oxide layer includes a gate insulating layer.

5 . The TFT as claimed in claim 4 , wherein the gate electrode is directly on the thermal oxide layer.

6 . The TFT as claimed in claim 1 , further comprising a buffer layer between the substrate and the semiconductor layer.

7 . The TFT as claimed in claim 6 , wherein the semiconductor layer is encapsulated between the buffer layer and the thermal oxide layer.

8 . A method of fabricating a thin film transistor (TFT), comprising:

forming a semiconductor layer on a substrate;

forming a thermal oxide layer on the semiconductor layer in an H 2 O atmosphere;

forming a gate electrode on the thermal oxide layer, the gate electrode positioned to correspond to a channel region of the semiconductor layer;

forming an interlayer insulating layer on the substrate; and

forming source and drain electrodes electrically connected to the semiconductor layer.

9 . The method as claimed in claim 8 , wherein forming the semiconductor layer includes crystallizing amorphous silicon to form a polysilicon layer and patterning the polysilicon layer.

10 . The method as claimed in claim 9 , wherein crystallizing the amorphous silicon layer includes using one or more of a solid phase crystallization (SPC) method, a sequential lateral solidification (SLS) method, an excimer laser annealing (ELA) method, a metal induced crystallization (MIC) method, and/or a metal induced lateral crystallization (MILC) method.

11 . The method as claimed in claim 10 , wherein after crystallizing and patterning the polysilicon layer, the thermal oxide layer is formed using annealing in an H 2 O atmosphere.

12 . The method as claimed in claim 8 , wherein forming the thermal oxide layer includes annealing the semiconductor layer in an H 2 O atmosphere.

13 . The method as claimed in claim 12 , wherein annealing the semiconductor layer includes using a rapid thermal annealing (RTA) method.

14 . The method as claimed in claim 12 , wherein annealing the semiconductor layer is performed at a temperature of about 550° C. to about 750° C.

15 . The method as claimed in claim 12 , wherein annealing the semiconductor layer includes setting the H 2 O atmosphere at a pressure of about 0.01 MPa to about 2 MPa.

16 . The method as claimed in claim 12 , wherein annealing the semiconductor layer includes forming the thermal oxide layer to a thickness of about 50 angstroms to about 300 angstroms.

17 . The method as claimed in claim 8 , further comprising forming a buffer layer between the substrate and the semiconductor layer.

18 . A display device, comprising:

a semiconductor layer on a substrate;

a thermal oxide layer on the semiconductor layer;

a gate electrode on the thermal oxide layer, the gate electrode positioned to correspond to a channel region of the semiconductor layer;

an interlayer insulating layer on the substrate;

source and drain electrodes electrically connected to the semiconductor layer; and

a light source electrically connected to one of the source and drain electrodes.

19 . The display device as claimed in claim 18 , wherein the thermal oxide layer includes silicon oxide.

20 . The display device as claimed in claim 18 , wherein the light source is an organic light emitting diode.