Spreading technique applied to broadband mobile communications by satelite relying on DVB-RCS
View Patent ↗A device (D 1 ) is dedicated to the processing of signals to be transmitted by waves, within a communication terminal (T). This device (D 1 ) includes i) memory (M 1 ) for temporarily storing a sequence of digital samples of an analogue input signal according to a first sampling frequency and in a manner synchronized with respect to starts of periodic time slots, and ii) digital/analogue conversion (CV 2 ) for generating, during each time slot and according to a second sampling frequency equal to N times the first sampling frequency, with N an integer strictly greater than 1, an analogue output signal, to be transmitted, representative of N repetitions of the sequence of digital samples that is stored in the memory (M 1 ) during the time slot concerned, so as to output the analogue signal according to a symbol rate equal to N times a reference symbol rate.
1. A device for processing signals to be transmitted by radio, comprising:
a buffer adapted to temporarily store a sequence of digital samples of an analog input signal at a first sampling frequency in sequence with the beginnings of periodic time slots, and
a digital-to-analog converter adapted to generate, during each time slot and at a second sampling frequency equal to N times the first sampling frequency where N is an integer strictly greater than 1, an analog output signal,
wherein the output signal represents N repetitions of the sequence of digital samples stored in the buffer during the time slot concerned and is transmitted at a symbol rate equal to N times a reference symbol rate.
2. A device according to claim 1 , further comprising clock controller adapted to convert reference clock signals at the first sampling frequency into working clock signals at the second sampling frequency and for feeding the digital-to-analog converter with the working clock signals so that they can operate at the second sampling frequency.
3. A device according to claim 1 , where, the digital-to-analog converter is adapted to reduce by a factor N the number of samples per symbol of the sequence of digital symbols repeated N times, whilst operating at the first sampling frequency, in the presence of a ratio between the first sampling frequency and the reference symbol rate greater than N.
4. A device according to claim 1 , further comprising a clock controller adapted to convert reference clock signals at the first sampling frequency into working clock signals at an intermediate frequency equal to J 1 times the first sampling frequency and less than the second sampling frequency, and for feeding the digital-to-analog converter with the working signals so that they can operate at the intermediate frequency, and in that the digital-to-analog converter is adapted to reduce by a factor K 1 the number of symbols per symbol of the sequence of digital samples repeated N times, where J 1 *K 1 =N, whilst operating at the intermediate frequency.
5. A device according to claim 1 , further comprising an analog-to-digital converter adapted to sample each analog input signal to be transmitted to produce a sequence of digital samples at the first sampling frequency in sequence with the beginnings of periodic time slots so as to feed sequences of samples to the buffer.
6. A device according to claim 5 , further comprising a first frequency conversion processor adapted to convert a primary frequency of the analog input signal into a secondary frequency before it feeds the analog-to-digital converter and a second frequency conversion processor adapted to convert the secondary frequency of the analog output signal into the primary frequency.
7. A device according to claim 6 , wherein the secondary frequency is a baseband frequency.
8. A radio communication terminal, further comprising a signal processing device according to claim 1 .
9. A device for processing analog signals coming from a signal processing device according to claim 1 , comprising:
an analog-to-digital converter adapted to sample an analog input signal representing N repetitions of sequences of digital samples, where N is an integer strictly greater than 1, to produce N identical sequences of digital samples at a third sampling frequency equal to N times a fourth sampling frequency in sequence with beginnings of periodic time slots,
a buffer adapted to store temporarily the N identical sequences of digital samples delivered by the analog-to-digital converter during each time slot, and
a combination processor adapted to combine in phase during each time slot the N identical sequences of digital samples stored in the buffer so as to deliver a sequence of digital samples combined at a reference symbol rate.
10. A device according to claim 9 , where the combination processor further comprises:
an estimation processor adapted to estimate the relative phase differences between the N identical sequences of digital samples,
wherein the compensation processor is adapted to compensate the estimated phase differences so as to deliver N identical compensated sequences, and
a summation processor adapted to sum the N identical sequences compensated so as to deliver the combined sequence of digital samples.
11. A device according to claim 9 ,
further comprising a clock controller adapted to convert reference clock signals at the fourth frequency into working clock signals at the third frequency and for feeding the analog-to-digital converter with the working signals so that they can operate at the fourth frequency.
12. A device according to claim 9 , wherein, the analog-to-digital converter is adapted to reduce by a factor N the number of samples per symbol of the N identical sequences of digital samples, whilst operating at the fourth sampling frequency, in the presence of a ratio between the fourth frequency and the reference symbol rate greater than N.
13. A device according to claim 9 , wherein:
the clock controller is adapted to convert reference clock signals at the fourth frequency into working clock signals at an intermediate frequency equal to J 2 times the fourth frequency and lower than the third frequency and for feeding the analog-to-digital converter with the working signals so that they can operate at the intermediate frequency, and
the analog-to-digital converter is adapted to reduce by a factor K 2 the number of samples per symbol of the N identical sequences of digital samples, where J 2 *K 2 =N, whilst operating at the intermediate frequency.
14. Device according to claim 9 , further comprising a digital-to-analog converter adapted to generate, during each time slot and at the fourth sampling frequency, an analog output signal representing the combined sequence of digital samples.
15. A device according to claim 14 , wherein the first frequency conversion processor is adapted to convert a primary frequency of the analog input signal into a secondary frequency before it feeds the analog-to-digital converter and the second frequency conversion processor adapted to convert the secondary frequency of the analog output signal to the primary frequency.
16. A device according to claim 15 , wherein the secondary frequency is baseband.
17. A device according to claim 9 , further comprising:
a demultiplexer located between the analog-to-digital converter and the buffer and adapted, in the presence of input signals on different carriers (Pi) associated with different numbers (Ni) of repetitions of values, for demultiplexing the repetitions of sequences as a function of the associated carriers,
where the buffer consist of storage modules each associated with one of the carriers and adapted to store the demultiplexed sequence repetitions that respectively correspond to them,
where the combination processor consists of combination modules each associated with one of the carriers and each adapted to combine in phase during each time slot the repetitions of identical sequences of digital samples stored in the corresponding storage module so as to deliver a combined sequence of digital samples at the reference symbol rate, and
a multiplexer downstream of the combination modules and adapted to multiplex the combined sequences of digital samples delivered by the combination modules so as to deliver multiplexes of sequences.
18. A demodulator of signals transmitted by radio, further comprising a signal processing device according to claim 9 .
19. A system for DVB-RCS type satellite communication comprising:
a first device comprising:
a buffer for temporarily storing a sequence of digital samples of an analog input signal according to a first sampling frequency and in a manner synchronized with respect to starts of periodic time slots, and
a digital-to-analog converter operative to generate, during each time slot and according to a second sampling frequency equal to N times the first sampling frequency, where N is an integer strictly greater than 1, an analog output signal representative of N repetitions of the sequence of digital samples that is stored in the buffer during the time slot concerned, transmitted according to a symbol rate equal to N times a reference symbol rate;
a second device, operative to process the analog signals output by the first device, including at least:
an analog-to-digital converter operative to sample an analog input signal representing N repetitions of sequences of digital samples, where N is an integer strictly greater than 1, to produce N identical sequences of digital samples at a third sampling frequency equal to N times a fourth sampling frequency in sequence with beginnings of periodic time slots,
a buffer operative to temporarily store the N identical sequences of digital samples delivered by analog-to-digital converter during each time slot, and
a combination processor, operative to combine in phase during each time slot the N identical sequences of digital samples stored in the buffer so as to deliver a sequence of digital samples combined at a reference symbol rate; and
a demodulator,
wherein the demodulator includes at least:
a digital-to-analog converter operative to generate from the output of the combination processor, in each time slot, and at a fourth sampling frequency, an analog output signal representing a combined sequence of digital signals,
a frequency conversion processor operative to convert to a primary frequency a secondary frequency of each analog output signal of the digital-to-analog converter, and
a carrier demodulation processor operative to demodulate the analog output of the frequency conversion processor.
20. A method for transmitting signals using a DVB-RCS type satellite communication standard comprising:
storing temporarily in a first buffer, in a first device, a sequence of digital samples of an analog input signal according to a first sampling frequency and in a manner synchronized with respect to starts of periodic time slots;
generating with a digital-to-analog converter, in a first device, during each time slot and according to a second sampling frequency equal to N times the first sampling frequency, where N is an integer strictly greater than 1, an analog output signal representative of N repetitions of the sequence of digital samples that is stored in the buffer during the time slot concerned, transmitted according to a symbol rate equal to N times a reference symbol rate;
sampling with an analog-to-digital converter, in a second device, an analog input signal representing N repetitions of sequences of digital samples, where N is an integer strictly greater than 1, to produce N identical sequences of digital samples at a third sampling frequency equal to N times a fourth sampling frequency in sequence with beginnings of periodic time slots;
temporarily storing in a second buffer, in a second device, the N identical sequences of digital samples delivered by analog-to-digital converter during each time slot;
combining with a combination processor, in a second device, in phase during each time slot, the N identical sequences of digital samples stored in the buffer so as to deliver a sequence of digital samples combined at a reference symbol rate;
generating with a digital-to-analog converter, in a demodulator, the output of the combination processor, in each time slot, and at a fourth sampling frequency, an analog output signal representing a combined sequence of digital signals;
converting with a frequency conversion processor, in a demodulator, to a primary frequency a secondary frequency of each analog output signal of the digital-to-analog converter; and,
demodulating with a carrier demodulation processor, in a demodulator, the analog output of the frequency conversion processor.