Low impedance polarity conversion circuit
A low impedance polarity conversion circuit for driving a load with a DC power source is disclosed. The DC power source has a first pole from which a first DC signal originates and a second pole from which a second DC signal originates. The first DC signal has a voltage greater than a voltage of the second DC signal. The conversion circuit includes a circuit output node through which an output DC signal is delivered from the conversion circuit to the load. The conversion circuit also includes a charge conditioning circuit for generating third and fourth DC signals. The third DC signal has a voltage greater than the first DC signal voltage and the fourth DC signal has a voltage less than the second DC signal voltage. A rectification circuit includes first and second inputs for attachment to the first pole and the second pole. A Field-Effect Transistor (FET) bridge is electrically connected to the first and second inputs. The FET bridge includes first and second pairs of cooperating FETs. The third voltage controls a first of the first pair of FETs and a first of the second pair of FETs. The fourth voltage controls a second of the first pair of FETs and a second of the second pair of FETs. The FET bridge is for rectifying the first and second DC signals in order that the output DC signal is the same polarity irrespective of whether the first input is attached to the first pole or the second pole.
1. A low impedance polarity conversion circuit for driving a load with a DC power source having a first pole from which a first DC signal originates and a second pole from which a second DC signal originates, the first DC signal having a voltage greater than a voltage of the second DC signal, the conversion circuit comprising:
a circuit output node through which an output DC signal is delivered from the conversion circuit to the load;
a charge conditioning circuit for generating third and fourth DC signals, said third DC signal having a voltage greater than the first DC signal voltage and said fourth DC signal having a voltage less than the second DC signal voltage;
a rectification circuit including:
first and second inputs for attachment to the first pole and the second pole; and
a transistor bridge electrically connected to said first and second inputs, said bridge including first and second pairs of cooperating transistors, said third voltage controlling a first of said first pair of transistors and a first of said second pair of transistors, and said fourth voltage controlling a second of said first pair of transistors and a second of said second pair of transistors, said bridge for rectifying the first and second DC signals in order that said output DC signal is the same polarity irrespective of whether said first input is attached to the first pole or the second pole.
2. The conversion circuit as claimed in claim 1 , wherein said transistor bridge is a Field Effect Transistor (FET) bridge and said transistors are FETs.
3. The conversion circuit as claimed in claim 1 , wherein said first pair of transistors are activated when said first and second inputs are attached to the first and second poles respectively, and said second pair of transistors are activated when said first and second inputs are attached to the second and first poles respectively.
4. The conversion circuit as claimed in claim 3 , wherein when said first pair of transistors are activated said second pair of transistors are non-activated, and when said second pair of transistors are activated said first pair of transistors are non-activated.
5. The conversion circuit as claimed in claim 4 , wherein said rectification circuit further includes a control circuit electrically connected to gates of each of said first and second pairs of transistors, said control circuit for making said generated third and fourth DC signals available to the activated pair of said pairs of transistors.
6. The conversion circuit as claimed in claim 5 , wherein said control circuit includes four level sensing transistors and four switching transistors.
7. The conversion circuit as claimed in claim 6 , wherein said level sensing transistors are P-channel transistors and said switching transistors are N-channel transistors.
8. The conversion circuit as claimed in claim 1 , wherein a voltage difference amount between said generated third and fourth DC signals is between two and four times a voltage difference amount between said first and second DC signals.
9. The conversion circuit as claimed in claim 1 , wherein said charge conditioning circuit includes a monostable multivibrator and a number of capacitors configured for voltage boosting and in communication with said monostable multivibrator, said monostable multivibrator for regulating charging of said capacitors.
10. The conversion circuit as claimed in claim 1 , wherein said generated third and fourth DC signals are substantially of equal and opposite magnitude.
11. The conversion circuit as claimed in claim 10 , wherein said charge conditioning circuit includes an inverter, said inverter including an input and an output, and when said third DC signal is received at said inverter input said fourth DC signal is outputted at said inverter output.