Integrated circuit and method of securing access to an on-chip memory
View Patent ↗An integrated circuit having an on-chip access right manager to grant or deny access to a memory segment to a peripheral device such as a CPU (Central Processing Unit), DSP (Digital Signal Processor) or DMA (Direct Memory Access) unit according to predetermined access rights upon reception of a read instruction from the peripheral device, and an on-chip lock connected to a memory data bus, the lock being controllable by the access right manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted. Upon reception of the read instruction from the peripheral device, the integrated circuit is configured to start both the process of setting, by the on chip memory, of either a logical one or a logical zero on each of the wires of the memo data bus, as well as the process of granting or refusing the access to the memory segment by the on-chip access right manager to the peripheral device.
1. An integrated circuit comprising:
an on-chip memory data bus having a plurality of conductive wires to communicate data stored in a memory to at least one of peripheral devices,
an on-chip memory connected to the memory data bus, the on-chip memory being controllable to set either a logical one or a logical zero on each of the wires of the memory data bus according to data stored in a memory segment, so that the data stored in the memory segment can be communicated to at least one peripheral device in response to a read instruction, the operation of setting either a logical one or a logical zero on each of the wires of the memory data bus corresponding to a memory access time interval
an on-chip access right manager to grant or deny access to the memory segment to the peripheral device according to predetermined access rights upon reception of a read instruction from the peripheral device, the operation of determining whether to grant or refuse access to the memory segment to the peripheral device corresponding to an assess time interval,
an on-chip lock connected to the memory data bus, the lock being controllable by the access right manager to block access to logical one or zero set on each memory data bus wire as long as the access to the memory segment is not granted,
wherein the integrated circuit is configured to start both the process of setting, by the on chip memory, of either a logical one or a logical zero on each of the wires of the memory data bus, as well as the process of deciding whether to grant or refuse the access to the memory segment by the on-chip access right manager to the peripheral device, upon reception of the read instruction from the peripheral device, wherein the process of setting either a logical one or a logical zero and the process of deciding whether to grant or refuse the access to the memory segment are performed at least partially at the same time, wherein the process of setting either a logical one o a logical zero is configured to begin before the process of deciding whether to grant or refuse the access to the memory segment, wherein the assess time interval is configured to end before the memory access time interval.
2. The integrated circuit according to claim 1 , wherein the lock is controllable by the access right manager to connect each wire of the memory data bus to a corresponding wire of an on-chip device data bus connected to a data input port of the peripheral device if access to the memory segment is granted.
3. The integrated circuit according to claim 2 , wherein the lock is controllable by the access right manager to set a dummy logical one or zero on each wire of the device data bus if access to the memory segment is denied.
4. The integrated circuit of claim 1 , wherein the process of setting either a logical one or a logical zero and the process of deciding whether to grant or refuse access to the memory segment are configured to begin at approximately the same time.
5. A method of securing access to an on-chip memory within an integrated circuit, the integrated circuit comprising an on-chip memory data bus having a plurality of conductive wires, wherein:
the on-chip memory sets either a logical one or a logical zero on each of the wires of the memory data bus according to data stored in a memory segment in view of communicating the stored data to a peripheral device upon reception of a read instruction from the peripheral device, the setting either a logical one or a logical zero on each of the wires of the memory data bus corresponding to a memory access time interval;
an on-chip access right manager decides whether to grant or deny access to the memory segment to the peripheral device according to predetermined access rights upon reception of the read instruction from the peripheral device the deciding whether to grant or deny access to the memory segment to the peripheral device corresponding to an assess time interval;
an on-chip lock connected to the memory data bus blocks access to logical one or zero set on each memory data bus wire as long as the access to the memory segment is not granted, and
wherein the assess time interval ends before the memory access time interval, and wherein the assess time interval and the memory access interval at least partially overlap, and wherein the memory access time interval begins prior to the assess time interval.
6. The method according to claim 5 , wherein the lock connects each wire of the memory data bus to a corresponding wire of an on-chip device data bus connected to the peripheral device if access to the memory segment is granted and, alternatively, the lock sets a dummy logical one or zero on each wire of the device data bus if access to the memory segment is denied.
7. The method according to claim 5 , wherein the assess time interval and the memory access time interval begin at approximately the same time.