LDMOS transistor
View Patent ↗The LDMOS transistor ( 1 ) of the invention comprises a source region ( 3 ), a channel region ( 4 ), a drain extension region ( 7 ) and a gate electrode ( 10 ). The LDMOS transistor ( 1 ) further comprises a first gate oxide layer ( 8 ) and a second gate oxide layer ( 9 ), which is thicker than the first gate oxide layer ( 8 ). The first gate oxide layer ( 8 ) at least extends over a first portion of the channel region ( 4 ), which is adjacent to the source region ( 3 ). The second gate oxide layer ( 9 ) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer ( 9 ) extends over a second portion of the channel region ( 4 ), which mutually connects the drain extension region ( 7 ) and the first portion of the channel region ( 4 ), thereby improving the linear efficiency of the LDMOS transistor ( 1 ).
1. An LDMOS transistor provided in a semiconductor substrate, the LDMOS transistor comprising a gate electrode, which extends over a channel region, a source region and a drain region being mutually connected through the channel region, the drain region comprising a drain contact region and a drain extension region extending from the drain contact region towards the channel region, the LDMOS transistor further comprising a first insulation layer, which at least extends over a first portion of the channel region adjacent to the source region, wherein a second insulation layer is provided laterally adjacent to the first insulation layer, the second insulation layer having a greater thickness than the first insulation layer, wherein at least a portion of the second insulation layer is at the same level as the first insulation layer, wherein the second insulation layer extends only over at least a portion of the drain extension region, wherein the gate electrode does not extend over the second insulation layer.
2. An LDMOS transistor as claimed in claim 1 further comprising a shield layer between the gate electrode and the drain contact region, the shield layer covering a part of the drain extension region.
3. An LDMOS transistor as claimed in claim 1 , wherein the drain extension region comprises a first and a second drain extension subregion, in which the first drain extension subregion has a higher dopant concentration than the second drain extension subregion and adjoins the channel region and the second drain extension subregion, which adjoins the drain contact region.
4. An LDMOS transistor as claimed in claim 1 wherein the shield layer and the second insulation layer both extend over the region where the first and the second drain extension subregion adjoin.
5. An LDMOS transistor as claimed in claim 2 wherein the shield layer has at least two stepped structure regions.
6. An LDMOS transistor as claimed in claim 2 wherein the shield layer comprises a metal silicide.
7. A method of manufacturing an LDMOS transistor, the method comprising:
providing a seed insulation layer on a semiconductor substrate;
removing selected portions of the seed insulation layer, thereby exposing portions of the semiconductor substrate;
forming a first insulation layer on the exposed portions of the semiconductor substrate and transforming the non-removed portions of the seed insulation layer into a second insulation layer adjoining the first insulation layer, in which the second insulation layer is thicker than the first insulation layer;
forming a gate electrode only on a portion of the first insulation layer; and
forming a source and a drain region, said drain region comprising a drain extension region, said second insulation layer extending only over at least a portion of the drain extension region.
8. An LDMOS transistor as claimed in claim 2 further comprising a third insulation layer disposed on top of the first insulating layer and the second insulating layer, said third insulating layer separating the shield layer from the gate electrode.
9. An LDMOS transistor as claimed in claim 1 wherein the first insulation layer further extends over a first portion of the drain extension region, and wherein the second insulation layer extends over a second portion of the drain extension region, wherein the first portion of the drain extension region adjoins the channel region, and the first portion of the drain extension region further adjoins the second portion of the drain extension region.
10. An LDMOS transistor as claimed in claim 9 wherein the channel region is directly adjacent to the first portion of the drain extension region, and the first portion of the drain extension region is directly adjacent to the second portion of the drain extension region.