Data receiver device and data transmission/reception system
View Patent ↗The data receiver device includes: a bit phase synchronizing circuit ( 10 ) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit ( 20 ) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit ( 10 ) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit ( 10 ) and a corresponding clock signal. The bit phase synchronizing circuit ( 10 ) initializes the phase adjustment of the data signal when receiving the detection signal.
1. A data receiver device for receiving a data signal to perform predetermined signal processing, comprising:
a bit phase synchronizing circuit for performing phase adjustment of the data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and
a state detection circuit for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit and a corresponding clock signal,
wherein the bit phase synchronizing circuit initializes the phase adjustment of the data signal when receiving the detection signal.
2. The data receiver device of claim 1 , wherein the state detection circuit outputs the detection signal once detecting a predetermined signal pattern in the phase-adjusted data signal.
3. The data receiver device of claim 2 , wherein the state detection circuit outputs the detection signal once detecting the predetermined signal pattern a plurality of times.
4. The data receiver device of claim 2 , wherein the state detection circuit outputs the detection signal once detecting the predetermined signal pattern at a predetermined period.
5. The data receiver device of claim 1 , further comprising an output control circuit for controlling output or not of the phase-adjusted data signal and the corresponding clock signal,
wherein the output control circuit controls the output of the phase-adjusted data signal and the corresponding clock signal when receiving the detection signal.
6. The data receiver device of claim 1 , further comprising a signal processing section for performing the predetermined signal processing based on the phase-adjusted data signal and the corresponding clock signal when receiving the detection signal.
7. The data receiver device of claim 1 , wherein the bit phase synchronizing circuit is a clock recovery circuit for generating the clock signal from the data signal.
8. The data receiver device of claim 1 , comprising a plurality of said bit phase synchronizing circuits,
wherein the state detection circuit outputs the detection signal once detecting that a data signal inputted into at least one of the plurality of bit phase synchronizing circuits is in a stable state based on a data signal phase-adjusted by the at least one bit phase synchronizing circuit and a corresponding clock signal.
9. The data receiver device of claim 8 , wherein the state detection circuit outputs the detection signal once detecting that all data signals inputted into the plurality of bit phase synchronizing circuits are in a stable state based on data signals phase-adjusted by the plurality of bit phase synchronizing circuits and corresponding clock signals.
10. The data receiver device of claim 8 , further comprising an output control circuit for controlling output or not of a plurality of data signals phase-adjusted by the plurality of bit phase synchronizing circuits and corresponding clock signals,
wherein the output control circuit controls the output of the plurality of phase-adjusted data signals and the corresponding clock signals when receiving the detection signal.
11. The data receiver device of claim 1 , wherein the stable state is a state in which the data signal has a desirable amplitude value and a jitter component falling within an allowable range.