Monolithically integrated III-nitride power converter
View Patent ↗A power arrangement that includes a monolithically integrated III-nitride power stage having III-nitride power switches and III-nitride driver switches.
1. A power management arrangement comprising:
a power stage that includes III-nitride power switches;
a driver stage that controls the operation of the power stage;
a load stage coupled to said power stage to receive power for the operation thereof, the load stage including a driver stage control circuitry to generate signals for the control of the operation of the driver stage.
2. The arrangement of claim 1 , wherein said III-nitride power switches arc coupled in a half-bridge arrangement.
3. The arrangement of claim 1 , wherein said III-nitride power switches are depletion mode devices.
4. The arrangement of claim 1 , wherein said driver stage includes a first pair of III-nitride switches arranged in a half-bridge for driving a first one of said III-nitride power switches and a second pair of III-nitride switches arranged in a half-bridge for driving a second one of said III-nitride power switches.
5. The arrangement of claim 4 , wherein said first pair of III-nitride switches and said second pair of switches are enhancement mode switches.
6. The arrangement of claim 4 , wherein said first pair of III-nitride switches and said second pair of III-nitride switches are depletion mode switches.
7. The arrangement of claim 5 , wherein said driver stage control circuitry generates pulse width modulation signals.
8. The arrangement of claim 6 , wherein said driver stage control circuitry generates pulse width modulation signals.
9. The arrangement of claim 1 , wherein said driver stage control circuitry generates pulse width modulation signals.
10. The arrangement of claim 1 , wherein said power stage and said driver stage are formed in a common die.
11. The arrangement of claim 1 , wherein said signals are generated when an output voltage of said power stage falls outside of a pre-set range.
12. The arrangement of claim 1 , wherein said signals are generated due to a load-specific condition.
13. The arrangement of claim 12 , wherein said load-specific condition includes the instantaneous temperature of said load.
14. The arrangement of claim 12 , wherein said load-specific condition includes the speed of said load.
15. The arrangement of claim 1 , wherein said load stage includes a microprocessor.
16. The arrangement of claim 1 , wherein said load stage includes a memory device.
17. A power management arrangement comprising:
a monolithic semiconductor die having formed therein a first III-nitride power semiconductor device and a second III-nitride power semiconductor device coupled to said first III-nitride power semiconductor device in a half-bridge configuration that includes an output node, a first driver half-bridge arrangement that is operatively coupled to said first III-nitride power semiconductor device, and a second driver half-bridge arrangement that is operatively coupled to said second III-nitride power semiconductor device.
18. The arrangement of claim 17 , wherein said first and second driver half-bridge arrangements each includes a pair of enhancement mode III-nitride switches.
19. The arrangement of claim 17 , wherein said first and second driver half-bridge arrangements each includes a pair of depletion mode III-nitride switches.
20. The arrangement of claim 17 , wherein said first driver half-bridge is coupled to a level shift circuit that includes a level shift capacitor, wherein said capacitor is formed on a surface of said monolithic semiconductor die.
21. The arrangement of claim 17 , wherein said output node is coupled to a load stage that includes driver control circuitry that generates signals for the operation of said first and second driver half-bridge arrangements.
22. The arrangement of claim 21 , wherein said driver stage control circuitry generates pulse width modulation signals.
23. The arrangement of claim 21 , wherein said signals are generated when an output voltage of said power stage falls outside of a pre-set range.
24. The arrangement of claim 21 , wherein said signals are generated due to a load-specific condition.
25. The arrangement of claim 24 , wherein said load-specific condition includes the instantaneous temperature of said load.
26. The arrangement of claim 24 , wherein said load-specific condition includes the speed of said load.
27. The arrangement of claim 17 , further comprising a load stage, wherein said load stage and said monolithic semiconductor die are integrated.
28. The arrangement of claim 27 , wherein said load stage includes a microprocessor.
29. The arrangement of claim 27 , wherein said load stage includes a memory device.