Time domain interpolation scheme for flash A/D converters
View Patent ↗An analog-to-digital converter circuit comprises a first voltage comparator coupled to a first reference voltage and a signal voltage, the first voltage comparator having first negative and first positive outputs for outputting a comparison of the first reference voltage with the signal voltage; a second voltage comparator coupled to a second reference voltage and the signal voltage, the second reference voltage different than the first reference voltage, the second voltage comparator having second negative and second positive outputs for outputting a comparison of the second reference voltage with the signal voltage; and a first arrival time comparator coupled to the first positive output and the second negative output, the first arrival time comparator having a first arrival time comparator output for outputting a comparison of the first positive output with the second negative output.
1. An analog-to-digital converter circuit comprising:
a first voltage comparator coupled to a first reference voltage and a signal voltage, the first voltage comparator having a first negative output and a first positive output for outputting a comparison of the first reference voltage with the signal voltage;
a second voltage comparator coupled to a second reference voltage and the signal voltage, the second reference voltage being different than the first reference voltage, the second voltage comparator having a second negative output and a second positive output for outputting a comparison of the second reference voltage with the signal voltage; and
a first arrival time comparator coupled to the first positive output and the second negative output, the first arrival time comparator having a first arrival time comparator output for outputting a comparison of the first positive output with the second negative output.
2. The analog-to-digital converter circuit of claim 1 further comprising:
a third voltage comparator coupled to a third reference voltage and the signal voltage, the third reference voltage being different than the first reference voltage and the second reference voltage, the third voltage comparator having a third negative output and a third positive output for outputting a comparison of the third reference voltage with the signal voltage; and
a second arrival time comparator coupled to the second positive output and the third negative output, the second arrival time comparator having a second arrival time comparator output for outputting a comparison of the second positive output with the third negative output.
3. The analog-to-digital converter circuit of claim 1 , further comprising:
a first delay coupled to the first positive output, the first delay having a first delay output for outputting the first positive output after a delay time; and
a second arrival time comparator coupled to the second negative output and the first delay output, the second arrival time comparator having a second arrival time comparator output for outputting a comparison of the second negative output with the first delay output.
4. The analog-to-digital converter circuit of claim 1 , further comprising:
a first delay coupled to the second negative output, the first delay having a first delay output for outputting the second negative output after a delay time; and
a second arrival time comparator coupled to the first positive output and the first delay output, the second arrival time comparator having a second arrival time comparator output for outputting a comparison of the first positive output with the first delay output.
5. The analog-to-digital converter circuit of claim 1 , further comprising:
a first delay coupled to the first positive output, the first delay having a first delay output for outputting the first positive output after a delay time;
a second delay coupled to the second negative output, the second delay having a second delay output for outputting the second negative output after a delay time;
a second arrival time comparator coupled to the first positive output and the second delay output, the second arrival time comparator having a second arrival time comparator output for outputting a comparison of the first positive output with the second delay output; and
a third arrival time comparator coupled to the second negative output and the first delay output, the third arrival time comparator having a third arrival time comparator output for outputting a comparison of the second negative output with the first delay output.
6. The analog-to-digital converter circuit of claim 1 , wherein the first voltage comparator is based on a regenerative latch, and the second voltage comparator is based on a regenerative latch.
7. The analog-to-digital converter circuit of claim 1 , wherein the first voltage comparator is based on a preamplifier followed by a regenerative latch, and the second voltage comparator is based on a preamplifier followed by a regenerative latch.
8. The analog-to-digital converter circuit of claim 1 , wherein the first voltage comparator is based on a plurality of cascaded regenerative latches, and the second voltage comparator is based on a plurality of cascaded regenerative latches.
9. The analog-to-digital converter circuit of claim 1 , wherein the first voltage comparator has a symmetric internal structure providing both positive and negative output signals, and the second voltage comparator has a symmetric internal structure providing both positive and negative output signals.
10. The analog-to-digital converter circuit of claim 1 , wherein the first arrival time comparator is a regenerative latch.
11. A method of analog-to-digital conversion comprising:
comparing a first reference voltage with a signal voltage;
outputting a first negative output and a first positive output based on comparing the first reference voltage with the signal voltage;
comparing a second reference voltage with the signal voltage, the second reference voltage being different than the first reference voltage;
outputting a second negative output and a second positive output based on comparing the second reference voltage with the signal voltage;
comparing the first positive output with the second negative output; and
outputting a first arrival time comparator output based on comparing the first positive output with the second negative output.
12. The method of analog-to-digital conversion of claim 11 , further comprising:
comparing a third reference voltage with the signal voltage, the third reference voltage being different than the first reference voltage and the second reference voltage;
outputting a third negative output and a third positive output based on comparing the third reference voltage with the signal voltage;
comparing the second positive output with the third negative output; and
outputting a second arrival time comparator output based on comparing the second positive output with the third negative output.
13. The method of analog-to-digital conversion of claim 11 , further comprising:
delaying the first positive output;
outputting a first delay output based on delaying the first positive output;
comparing the first delay output with the second negative output; and
outputting a second arrival time comparator output based on comparing the first delay output with the second negative output.
14. The method of analog-to-digital conversion of claim 11 , further comprising:
delaying the second negative output;
outputting a first delay output based on delaying the second negative output;
comparing the first delay output with the first positive output; and
outputting a second arrival time comparator output based on comparing the first delay output with the first positive output.
15. The method of analog-to-digital conversion of claim 11 , further comprising:
delaying the first positive output;
outputting a first delay output based on delaying the first positive output;
comparing the first delay output with the second negative output;
outputting a second arrival time comparator output based on comparing the first delay output with the second negative output;
delaying the second negative output;
outputting a second delay output based on delaying the second negative output;
comparing the second delay output with the first positive output; and
outputting a third arrival time comparator output based on comparing the second delay output with the first positive output.
16. The method of analog-to-digital conversion of claim 11 , wherein the comparison of the first reference voltage with the signal voltage is performed by a first voltage comparator based on a regenerative latch, and the comparison of the second reference voltage with the signal voltage is performed by a second voltage comparator based on a regenerative latch.
17. The method of analog-to-digital conversion of claim 11 , wherein the comparison of the first reference voltage with the signal voltage is performed by a first voltage comparator based on a preamplifier followed by a regenerative latch, and the comparison of the second reference voltage with the signal voltage is performed by a second voltage comparator based on a preamplifier followed by a regenerative latch.
18. The method of analog-to-digital conversion of claim 11 , wherein the comparison of the first reference voltage with the signal voltage is performed by a first voltage comparator based on a plurality of cascaded regenerative latches, and the comparison of the second reference voltage with the signal voltage is performed by a second voltage comparator based on a plurality of cascaded regenerative latches.
19. The method of analog-to-digital conversion of claim 11 , wherein the comparison of the first reference voltage with the signal voltage is performed by a first voltage comparator that has a symmetric internal structure providing both positive and negative output signals, and the comparison of the second reference voltage with the signal voltage is performed by a second voltage comparator that has a symmetric internal structure providing both positive and negative output signals.
20. An analog-to-digital converter circuit comprising:
a first voltage comparator coupled to a first reference voltage and a signal voltage, the first voltage comparator having a first positive output for outputting a comparison of the first reference voltage with the signal voltage;
a second voltage comparator coupled to a second reference voltage and the signal voltage, the second reference voltage being different than the first reference voltage, the second voltage comparator having a second negative output for outputting a comparison of the second reference voltage with the signal voltage; and
a first arrival time comparator coupled to the first positive output and the second negative output, the first arrival time comparator having a first arrival time comparator output for outputting a comparison of the first positive output with the second negative output.