Method for fabricating semiconductor device
View Patent ↗In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.
1. A method for fabricating a semiconductor device comprising:
forming device isolation structures in a capacitor region of a silicon substrate;
forming a bottom electrode and a dielectric layer on a first device isolation structure;
forming a capping oxide layer and a nitride layer on an entire surface of the silicon substrate including the bottom electrode, and performing a blanket etchback process on the capping oxide layer and the nitride layer to form insulation sidewalls on sides of the bottom electrode;
simultaneously forming a top electrode on the dielectric layer and a gate electrode in a transistor region of the silicon substrate, wherein the top electrode has a width less than a width of the bottom electrode; and
forming source/drain impurity regions in the silicon substrate at sides of the gate electrode.
2. The method according to claim 1 , wherein the dielectric layer comprises an oxide-nitride-oxide structure.
3. The method of claim 1 , wherein the dielectric layer comprises an oxide layer including a transition element and a rare-earth element.
4. The method of claim 3 , wherein the dielectric layer comprises BaTiO 3 , PbTiO 3 , or SrTiO 3 .
5. The method of claim 4 , wherein the well region is formed after forming the insulation sidewalls and before forming the gate electrode.
6. The method according to claim 1 , further comprising implanting ions into the transistor region of the silicon substrate to form a well region.
7. The method of claim 1 , wherein forming the bottom electrode comprises forming a first polysilicon layer over the entire silicon substrate.
8. The method of claim 7 , wherein the dielectric layer is deposited over the entire first polysilicon layer.
9. The method of claim 8 , wherein forming the bottom electrode comprises patterning the dielectric layer and the first polysilicon layer.
10. The method of claim 9 , wherein patterning the dielectric layer and the first polysilicon layer simultaneously forms resistors on second device isolation structures in a transistor region and in a capacitor region.
11. The method of claim 1 , further comprising forming resistors on each of second device isolation structures in a transistor region and in a capacitor region of the substrate.
12. The method of claim 1 , further comprising forming a gate oxide layer in a transistor region of the silicon substrate prior to forming the top electrode and the gate electrode.
13. The method of claim 12 , wherein the gate electrode is formed on the gate oxide layer.
14. The method of claim 1 , wherein forming the top electrode comprises forming a second polysilicon layer over the entire silicon substrate.
15. The method of claim 14 , wherein forming the top electrode comprises patterning the second polysilicon layer.
16. The method of claim 14 , wherein patterning the second polysilicon layer simultaneously forms resistors on a second device isolation structure in a transistor region and in a capacitor region.
17. The method of claim 1 , further comprising annealing the silicon substrate after forming the bottom electrode.
18. The method of claim 1 , wherein forming source/drain impurity regions comprises implanting ions into the substrate in the transistor region using the gate electrode as a mask.