Digital-to-analog converter and digital-to-analog conversion method thereof
View Patent ↗A digital-to-analog converter (DAC) can minimize the increase of an area caused by increase of number of bits. The DAC includes a coarse resistor-string digital-to-analog conversion unit for selectively outputting 2 N -level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2, a fine resistor-string digital-to-analog conversion unit for selectively outputting 2 N -level analog voltages in response to lower N-bit digital data, wherein the 2 N -level analog voltages is obtained by dividing a level of unit voltage of the coarse resistor-string digital-to-analog conversion unit into 2 N -levels, and a voltage combining unit for outputting 2 2N -level analog output signals by combining the output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to-analog conversion unit.
1. A digital-to-analog converter, comprising:
a coarse resistor-string digital-to-analog conversion unit for selectively outputting one of the 2 N -level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2;
a fine resistor-string digital-to-analog conversion unit for selectively outputting one of the 2 N -level analog voltages in response to lower N-bit digital data, the 2 N -level analog voltages being obtained by dividing a level of unit voltage of the coarse resistor-string digital-to-analog conversion unit into 2 N levels; and
a voltage combining unit including:
a capacitor,
a switching circuit configured to provide a plurality of capacitive couplings by switching the connection of first and second nodes of the capacitor, a coarse analog voltage terminal of the coarse resistor-string digital-to-analog conversion unit, a lowest reference voltage terminal; and
a fine analog voltage terminal of the fine resistor-string digital-to-analog conversion unit and a unit gain buffer circuit configured to buffer a voltage generated by the capacitive coupling and output the 2 2N -level analog output signals,
wherein the unit gain buffer circuit has a positive input terminal connected to the first node of the capacitor and a negative input terminal feedback-connected to an output terminal of the unit gain buffer circuit.
2. The digital-to-analog converter as recited in claim 1 , wherein the coarse resistor-string digital-to-analog conversion unit includes:
2 N resistors serially connected between a lowest reference voltage terminal and a highest reference voltage terminal and configured to divide a highest reference voltage into 2 N -level coarse division voltages; and
a first decoder configured to select one of the 2 N -level coarse division voltages according to the upper N-bit digital data.
3. The digital-to-analog converter as recited in claim 2 , wherein the fine resistor-string digital-to-analog conversion unit includes:
2 N resistors serially connected between the lowest reference voltage terminal and a unit voltage terminal of the coarse resistor-string digital-to-analog conversion unit and configured to divide the unit voltage into 2 N -level fine division voltages; and
a second decoder configured to select one of the 2 N -level fine division voltages according to the lower N-bit digital data.
4. The digital-to-analog converter as recited in claim 1 , wherein the switching circuit includes:
a first switch disposed between the second node of the capacitor and the coarse analog voltage terminal;
a second switch disposed between the second node of the capacitor and the lowest reference voltage terminal; and
a third switch disposed between the first node of the capacitor and the fine analog voltage terminal.
5. A digital-to-analog converter, comprising:
a coarse resistor-string digital-to-analog conversion unit for selectively outputting one of the 2 N -level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2;
a fine resistor-string digital-to-analog conversion unit for selectively outputting one of the 2 N -level analog voltages in response to lower N-bit digital data, the 2 N -level analog voltages being obtained by dividing a level of unit voltage of the coarse resistor-string digital-to-analog conversion unit into 2 N levels; and
a voltage combining unit including a capacitor, a switching circuit configured to provide a plurality of capacitive couplings by switching the connection of first and second nodes of the capacitor, a coarse analog voltage terminal of the coarse resistor-string digital-to-analog conversion unit, the lowest reference voltage terminal, and a fine analog voltage terminal of the fine resistor-string digital-to-analog conversion unit and a unit gain buffer circuit configured to buffer a voltage generated by the capacitive coupling and output the 2 2N -level analog output signals,
wherein a negative input terminal of the unit gain buffer is connected to the first node of the capacitor and the switching circuit includes a first switch disposed between the first node of the capacitor and an output terminal of the unit gain buffer circuit, a second switch disposed between the second node of the capacitor and the lowest reference voltage terminal, a third switch disposed between the second node of the capacitor and the output terminal of the unit gain buffer circuit, a fourth switch disposed between a positive input terminal of the unit gain buffer circuit and the fine analog voltage terminal and a fifth switch disposed between the positive input terminal of the unit gain buffer circuit and the coarse analog voltage terminal.