Thin film transistor array substrate and method for fabricating same
View Patent ↗An exemplary TFT array substrate includes: an insulating substrate ( 201 ), a gate line ( 23 ) and a repair structure ( 272 ) arranged on the insulating substrate, a gate insulating layer ( 204 ) covering the gate line and the repair structure; a data line ( 27 ) arranged on the gate insulating layer corresponding to the repair structure, which is insulated from the gate line and intersects with the gate line. The repair structure has a gap ( 274 ). The gap of the repair structure is located at where the repair structure overlapping to the gate line.
1. A method for fabricating a thin film transistor (TFT) array substrate, the method comprising:
providing an insulating substrate;
forming a common electrode on the insulating substrate and a repair structure on the insulating substrate by a first photolithograph process, the repair structure having a plurality of gaps;
forming a common line, a gate line, and a gate electrode on the insulating substrate by a second photolithograph process, the gate electrode being connected to the gate line;
forming a gate insulating layer and a semiconductor layer on the gate insulating layer by a third photolithograph process, the semiconductor layer being above the gate electrode; and
forming a data line and source/drain electrodes on the gate insulating layer by a fourth photolithograph process, the data line being above the repair structure and intersecting with the gate line and the common line, wherein the gaps of the repair structure each correspond to an overlap of the gate line and the repair line, or an overlap of the common line and repair line.
2. The method as claimed in claim 1 , further comprising forming a passivation material layer by a fifth photolithograph process, the passivation layer being provided between the common electrode and the gate line, and between the gate line and the common line.
3. The method as claimed in claim 1 , further comprising forming a pixel electrode on the passivation material layer by a sixth photolithograph process.
4. The method as claimed in claim 1 , wherein the common line is parallel to and adjacent to the gate line.
5. The method as claimed in claim 1 , wherein the common line is connected to the common electrode in order to provide common voltage signals thereto.
6. The method as claimed in claim 1 , wherein the fifth photolithograph process comprises coating a photo-resist layer on the insulating substrate on the passivation material layer, exposing the photo-resist layer using a photo-mask, and developing the exposed photo-resist layer to form a photo-resist pattern.
7. The method as claimed in claim 6 , wherein the fifth photolithograph process further comprises etching the passivation material layer which is above the drain electrode, thereby forming a through hole therein.
8. The method as claimed in claim 7 , wherein the drain electrode is electrically connected to the pixel electrode by the through hole.
9. The method as claimed in claim 1 , wherein the data line is parallel to the repair structure.
10. The method as claimed in claim 1 , wherein a width of the repair structure is equal to a width of the data line, or equal to half of a width of the data line.
11. The method as claimed in claim 1 , wherein the insulating substrate is made from glass or quartz.
12. The method as claimed in claim 1 , wherein the common electrode and pixel electrode are made from indium-tin-oxide or indium-zinc-oxide.
13. The method as claimed in claim 1 , wherein the gate electrode, the gate line, and the common line are made from material including any one or more items selected from the group consisting of aluminum, molybdenum, copper, chromium, and tantalum.
14. The method as claimed in claim 1 , wherein the source/drain electrodes are made from material including any one or more items selected from the group consisting of aluminum, aluminum alloy, molybdenum, tantalum, and molybdenum-tungsten alloy.
15. A thin film transistor array substrate comprising:
an insulating substrate;
a gate line and a repair structure provided on the insulating substrate, the repair structure having a gap;
a gate insulating layer covering the gate line and the repair structure;
a data line arranged on the gate insulating layer corresponding to the repair structure, which is insulated from the gate line and intersects with the gate line;
wherein the gap of the repair structure is located at where the repair structure overlapping the gate line.
16. The thin film transistor array substrate as claimed in claim 15 , further comprising a common line parallel to the data line and a common electrode arranged on the insulating substrate, the common electrode being electrically connected to the common line in order to provide a common voltage signal thereto.
17. The thin film transistor array substrate as claimed in claim 16 , wherein the repair structure further comprises a gap located at where the repair structure overlapping to the common line.
18. The thin film transistor array substrate as claimed in claim 17 , further comprising a pixel electrode corresponding to the common electrode, the pixel electrode being insulated from the common electrode.
19. The thin film transistor array substrate as claimed in claim 15 , wherein a width of the repair structure is equal to a width of the data line.
20. The thin film transistor array substrate as claimed in claim 18 , further comprising a thin film transistor arranged at a vicinity of an intersection of the gate line and the data line, the thin film transistor comprising a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode.