Programmable power supervisor
View Patent ↗A programmable power-on reset circuit in accordance with one embodiment of the invention can include a programmable voltage divider. The programmable power-on reset circuit can also include a comparator that is coupled to the programmable voltage divider and that is coupled to receive a reference voltage. Additionally, the programmable power-on reset circuit can include a non-volatile memory that is coupled to the programmable voltage divider, wherein the non-volatile memory can be coupled to receive programming for controlling an output of the programmable voltage divider.
1. A programmable power-on reset circuit comprising:
a programmable voltage divider;
a comparator coupled to the programmable voltage divider and coupled to receive a reference voltage;
a non-volatile memory coupled to the programmable voltage divider, the non-volatile memory coupled to receive programming for controlling an output of the programmable voltage divider; and
a delay module coupled to the comparator and the non-volatile memory.
2. The programmable power-on reset circuit of claim 1 , wherein the programming sets a delay period of the delay module.
3. A programmable power-on reset circuit comprising:
a programmable voltage divider;
a comparator coupled to the programmable voltage divider and coupled to receive a reference voltage;
a non-volatile memory coupled to the programmable voltage divider, the non-volatile memory coupled to receive programming for controlling an output of the programmable voltage divider; and
a glitch detection module coupled to the comparator and the non-volatile memory.
4. The programmable power-on reset circuit of claim 3 , wherein the programming sets a glitch detection interval for the glitch detection module.
5. A programmable power-on reset circuit comprising:
programmable voltage divider;
a comparator coupled to the programmable voltage divider and coupled to receive a reference voltage; and
a processing element coupled to the programmable voltage divider, the processing element coupled to receive programming for controlling an output of the programmable voltage divider; and
a non-volatile memory coupled to the processing element, the non-volatile memory for storing the programming.
6. The programmable power-on reset circuit of claim 5 , wherein the processing element generates a reset signal.
7. The programmable power-on reset circuit of claim 5 , wherein the programming sets a delay period implemented by the processing element.
8. The programmable power-on reset circuit of claim 5 , wherein the programming sets a glitch detection interval implemented by the processing element.
9. The programmable power-on reset circuit of claim 5 , wherein the processing element is coupled to the comparator.
10. A method comprising:
receiving an input voltage;
storing programming data with non-volatile memory, the programming data sets a threshold reference voltage; and
outputting a reset signal if the input voltage falls below the threshold reference voltage,
wherein the programming data sets a delay period associated with the outputting the reset signal.
11. The method of claim 10 , wherein the programming data sets a glitch rejection period associated with the outputting the reset signal.