IP Library Granted Patent US 7,898,609
Granted Patent B2
US 7,898,609 · App. 12/005,941 · Granted Mar 1, 2011

Multi-domain vertical alignment liquid crystal display having dielectric medium with nonuniform thickness

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,898,609
App. No.
12/005,941
Granted
Mar 1, 2011
Kind
B2
Abstract

An exemplary MVA LCD ( 2 ) includes a first substrate ( 21 ), a second substrate ( 22 ), and a liquid crystal layer ( 23 ) interposed between the two substrates. A common electrode ( 29 ) and protrusions ( 211 ) are formed at an inner side of the first substrate in order. Gate electrodes ( 221 ) and pixel electrodes ( 222 ) are formed on an inner side of the second substrate. A patterned gate insulating layer ( 223 ) is formed at the second substrate. The patterned gate insulating layer covers the gate electrodes, and a part of each pixel electrode.

Claims (31)

1. A multi-domain vertical alignment (MVA) liquid crystal display (LCD), comprising:

a first substrate;

a common electrode formed at an inner side of the first substrate;

a plurality of protrusions formed on the common electrode;

a second substrate parallel to the first substrate;

a liquid crystal layer between the two substrates;

a plurality of gate electrodes and pixel electrodes formed at an inner side of the second substrate; and

a patterned gate insulating layer formed at the inner side of the second substrate, the patterned gate insulating layer covering the gate electrodes, and a part of each pixel electrode.

2. The MVA LCD as claimed in claim 1 , wherein the pixel electrodes comprise a plurality of recesses corresponding to the plurality of protrusions.

3. The MVA LCD as claimed in claim 2 , wherein a passivation layer is formed on the thin film transistors and the pixel electrodes.

4. The MVA LCD as claimed in claim 3 , further comprising a first alignment film formed on the common electrode and the protrusions.

5. The MVA LCD as claimed in claim 4 , further comprising a second alignment film formed on the passivation layer.

6. The MVA LCD as claimed in claim 1 , further comprising a first polarization film disposed at an outer side of the first substrate.

7. The MVA LCD as claimed in claim 6 , further comprising a second polarization film disposed at an outer side of the second substrate.

8. The MVA LCD as claimed in claim 7 , wherein a polarization axis of the first polarization film is perpendicular to a polarization axis of the second polarization film.

9. The MVA LCD as claimed in claim 1 , further comprising a color filter formed between the first substrate and the common electrode.

10. The MVA LCD as claimed in claim 1 , further comprising a semiconductor layer, a source electrode, and a drain electrode formed at each of the gate electrodes, wherein the semiconductor layer defines a groove, and the source electrode and the drain electrode are formed on the semiconductor layer at two sides of the groove.

11. The MVA LCD as claimed in claim 10 , wherein the drain electrode is connected to a corresponding one of the pixel electrodes.

12. The MVA LCD as claimed in claim 1 , wherein the gate insulating layer is made of silicon oxide (SiO 2 ).

13. A multi-domain vertical alignment (MVA) liquid crystal display (LCD), comprising:

a first substrate;

a common electrode formed at an inner side of the first substrate;

a plurality of protrusions formed on the common electrode;

a second substrate parallel to the first substrate;

a liquid crystal layer between the two substrates; and

a plurality of thin film transistors and pixel electrodes formed at an inner side of the second substrate, wherein each of the thin film transistors, a corresponding one of the pixel electrodes, the common electrode, and the liquid crystal layer define a pixel, and a dielectric medium layer is formed at the pixel electrode, the dielectric medium layer configured to facilitate the generation of an electric field having various electric field lines when a voltage is applied to the pixel.

14. The MVA LCD as claimed in claim 13 , wherein each of the thin film transistors comprises a gate electrode and a gate insulating layer formed at the inner side of the second substrate, a semiconductor layer formed on the gate insulating layer corresponding to the gate electrode, a source electrode, and a drain electrode.

15. The MVA LCD as claimed in claim 14 , wherein the dielectric medium layer is made from a same material as the gate insulating layer.

16. The MVA LCD as claimed in claim 15 , wherein the dielectric medium layer is made from silicon oxide (SiO 2 ).

17. The MVA LCD as claimed in claim 13 , further comprising a first alignment film formed on the common electrode.

18. The MVA LCD as claimed in claim 17 , further comprising a passivation layer formed on the thin film transistors and the pixel electrodes, and a second alignment film formed on the passivation layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2024
From: INNOLUX CORPORATION
To: RED OAK INNOVATIONS LIMITED
Reel/Frame 069206/0903 →
CHANGE OF NAME Recorded Apr 7, 2014
From: CHIMEI INNOLUX CORPORATION
To: INNOLUX CORPORATION
Reel/Frame 032621/0718 →
CHANGE OF NAME Recorded Dec 8, 2010
From: INNOLUX DISPLAY CORP.
To: CHIMEI INNOLUX CORPORATION
Reel/Frame 025468/0200 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2007
From: HUANG, SHANG-YU; HUNG, CHAO-YI; HSIEH, TSAU-HUA
To: INNOLUX DISPLAY CORP.
Reel/Frame 020365/0720 →