IP Library Granted Patent US 7,728,670
Granted Patent B1
US 7,728,670 · App. 12/006,141 · Granted Jun 1, 2010

Method and apparatus for an amplifier

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Quick Facts
Patent No.
US 7,728,670
App. No.
12/006,141
Granted
Jun 1, 2010
Kind
B1
Abstract

An amplifier including complementary push and pull components, a bias component and a quiescent current balancer. The complementary push and pull components are serially coupled to one another between an electrical source and sink to generate an output signal at a common output terminal responsive to the input signal source. The bias component is coupled between the input signal source and the complementary push-pull components to bias the input signal to the push component and the input signal to the pull component by discrete amounts which reduce cross-over clipping exhibited in the output signal. The quiescent current balancer is coupled to the output terminal to balance quiescent currents in the push and the pull component at discrete levels which equilibrate amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.

Claims (52)

1. An amplifier for amplifying an input signal from an input signal source, and the amplifier comprising:

complementary push and pull components having control inputs coupled to the input signal source and channels serially coupled to one another between an electrical source and sink to generate an output signal at a common output terminal there between responsive to the input signal source;

a bias component coupled between the input signal source and the control inputs of the complementary push-pull components to bias the input signal to the push component and the input signal to the pull component by discrete amounts which reduce cross-over clipping exhibited in the output signal at the output terminal; and

a quiescent current balancer coupled to the complementary pull components exclusively at the common output terminal thereof and without any connection to the control inputs of the complementary push and pull components to balance quiescent currents in the push and the pull component at discrete levels which equilibrate amplification levels of the input signal generated by the push component and the pull component in the output signal at the common output terminal; thereby reducing distortion in output signal.

2. The amplifier of claim 1 , wherein the quiescent current balancer further comprises:

a high impedance electrical sink which removes a fixed amount of the quiescent current between the push component and the pull component at the output terminal thereby lowering quiescent current levels in the pull component relative to the push component by an amount which substantially equilibrates amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.

3. The amplifier of claim 1 , wherein the quiescent current balancer further comprises:

a high impedance electrical source which adds a fixed amount of current to the quiescent current between push component and the pull component at the output terminal thereby raising quiescent current levels in the pull component relative to the push component by an amount which substantially equilibrates amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.

4. The amplifier of claim 1 , wherein the quiescent current balancer further comprises:

a current mirror coupled to the output terminal and operative as a selected one of an electrical source and an electrical sink to adjust quiescent current levels in the push component and the pull component relative to one another by an amount which substantially equilibrates amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.

5. The amplifier of claim 1 , wherein the complementary push and pull components further comprise:

complementary “N” and “P” transistor types operating in anti-phase with one another responsive to the input signal to generate the output signal at the output terminal.

6. The amplifier of claim 1 , wherein the complementary push and pull components further comprise:

a push component having a pair of complementary “N” and “P” type bipolar transistors coupled in parallel between a voltage source and the output terminal to provide two stages of amplification of the input signal at the output terminal; and

a pull component having a pair of complementary “P” and “N” type bipolar transistors coupled in parallel between the output terminal and a voltage sink and operating in anti-phase with respect to the push component to provide two stages of amplification of the input signal at the output terminal.

7. An amplifier for amplifying an input signal from an input signal source, and the amplifier comprising:

complementary push and pull components serially coupled to one another between an electrical source and sink to generate an output signal at a common output terminal there between responsive to the input signal source;

a bias component coupled between the input signal source and the complementary push-pull components to bias the input signal to the push component and the input signal to the pull component by discrete amounts which reduce cross-over clipping exhibited in the output signal at the output terminal;

a quiescent current balancer coupled to the output terminal of the complementary push and pull components to balance quiescent currents in the push and the pull component at discrete levels which equilibrate amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal; and the quiescent current balancer including:

a programmable current mirror coupled to the output terminal and operative as a selected one of an electrical source and an electrical sink to adjust quiescent current levels in the push component and the pull component relative to one another by an amount which substantially equilibrates amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal and the current mirror further responsive to a program signal to incrementally re-adjust quiescent current levels in the push component and the pull component in a direction which improves equilibration of the amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.

8. A method for amplifying an input signal from an input signal source, and the method comprising:

pushing current from an electrical source to an output terminal responsive to a first phase of the input signal to generate a corresponding portion of the output signal at the output terminal;

pulling current to an electrical sink from the output terminal responsive to a second phase of the input signal substantially complementary to the first phase to generate a remaining corresponding portion of the output signal at the output terminal;

biasing the input signal to the pulling act and the input signal to the pushing act by discrete amounts which reduce cross-over clipping exhibited in the output signal at the output terminal; and

balancing quiescent currents exclusively at the output terminal at discrete levels which equilibrate amplification levels of the input signal generated by the pushing act and the pulling act in the output signal at the output terminal, thereby avoiding further biasing of the input signal biased in the biasing act and reducing distortion in the output signal.

9. The method for amplifying of claim 8 wherein the balancing act further comprises:

providing a current mirror coupled to the output terminal and operative as a selected one of an electrical source and an electrical sink to adjust quiescent current levels by an amount which substantially equilibrates amplification levels of the input signal generated by the pushing and pulling acts in the output signal at the output terminal.

10. The method for amplifying of claim 8 wherein the pushing and pulling acts further comprise:

providing a selected one of an “N” and a “P” type transistor to perform the pulling act; and

providing a remaining unselected one of the “N” and “P” type transistor to perform the pushing act.

11. A method for amplifying an input signal from an input signal source, and the method comprising:

pushing current from an electrical source to an output terminal responsive to a first phase of the input signal to generate a corresponding portion of the output signal at the output terminal;

pulling current to an electrical sink from the output terminal responsive to a second phase of the input signal substantially complementary to the first phase to generate a remaining corresponding portion of the output signal;

biasing the input signal to the pulling act and the input signal to the pushing act by discrete amounts which reduce cross-over clipping exhibited in the output signal at the output terminal;

balancing quiescent currents in the pushing act and the pulling act at discrete levels which equilibrate amplification levels of the input signal generated by the pushing act and the pulling act in the output signal at the output terminal; and the balancing act further includes;

providing a programmable current mirror coupled to the output terminal and operative as a selected one of an electrical source and an electrical sink to adjust quiescent current levels in the pushing act and the pulling act relative to one another by an amount which substantially equilibrates amplification levels of the input signal generated by the pushing and pulling acts at the output terminal and the current mirror further responsive to a program signal to incrementally re-adjust quiescent current levels in the pushing and pulling acts in a direction which improves equilibration of the amplification levels of the input signal generated by the pushing and pulling acts in the output signal at the output terminal.

12. A means for amplifying an input signal from an input signal source, and the means comprising:

means for pushing current from a electrical source to an output terminal responsive to a first phase of the input signal to generate an output signal at the output terminal;

means for pulling current to an electrical sink from the output terminal responsive to a second phase of the input signal substantially complementary to the first phase to generate a remaining portion of the output signal at the output terminal;

means for biasing the input signal to the means for pulling and the input signal to the means for pushing by discrete amounts which reduce cross-over clipping exhibited in the output signal at the output terminal; and

means for balancing quiescent currents exclusively at the output terminal at discrete levels which equilibrate amplification levels of the input signal generated by the pushing means and the pulling means in the output signal at the output terminal, thereby avoiding further biasing of the input signal biased by the biasing means and reducing distortion in the output signal.

13. The means for amplifying of claim 12 wherein the balancing means further comprises:

means for providing a current mirror coupled to the output terminal and operative as a selected one of an electrical source and an electrical sink to adjust quiescent current levels by an amount which substantially equilibrates amplification levels of the input signal generated by the pushing and pulling means in the output signal at the output terminal.

14. The means for amplifying of claim 12 wherein the pushing and pulling means further comprise:

means for providing a selected one of an “N” and a “P” type transistor to implement the pulling means; and

means for providing a remaining unselected one of the “N” and “P” type transistor to implement the pushing means.

15. A means for amplifying an input signal from an input signal source, and the means comprising:

means for pushing current from a electrical source to an output terminal responsive to a first phase of the input signal to generate an output signal at the output terminal;

means for pulling current to an electrical sink from the output terminal responsive to a second phase of the input signal substantially complementary to the first phase to generate a remaining portion of the output signal;

means for biasing the input signal to the means for pulling and the input signal to the means for pushing by discrete amounts which reduce cross-over clipping exhibited in the output signal at the output terminal;

means for balancing quiescent currents in the pushing means and the pulling means at discrete levels which equilibrate amplification levels of the input signal generated by the pushing means and the pulling means in the output signal at the output terminal and wherein the balancing means further includes:

means for providing a programmable current mirror coupled to the output terminal and operative as a selected one of an electrical source and an electrical sink to adjust quiescent current levels in the pushing means and the pulling means relative to one another by an amount which substantially equilibrates amplification levels of the input signal generated by the pushing and pulling means at the output terminal and the current mirror further responsive to a program signal to incrementally re-adjust quiescent current levels in the pushing and pulling means in a direction which improves equilibration of the amplification levels of the input signal generated by the pushing and pulling means in the output signal at the output terminal.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Sep 30, 2015
From: ALCATEL-LUCENT USA, INC.
To: IKANOS COMMUNICATIONS, INC.
Reel/Frame 036732/0876 →
RELEASE OF SECURITY INTEREST Recorded Sep 30, 2015
From: SILICON VALLEY BANK
To: IKANOS COMMUNICATIONS, INC.
Reel/Frame 036733/0031 →
SECURITY INTEREST Recorded Jun 10, 2015
From: IKANOS COMMUNICATIONS, INC.
To: SILICON VALLEY BANK
Reel/Frame 035874/0351 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded May 5, 2015
From: IKANOS COMMUNICATIONS, INC.
To: ALCATEL-LUCENT USA, INC.
Reel/Frame 035581/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2008
From: KIM, CHUN-SUP
To: IKANOS COMMUNICATIONS INC.
Reel/Frame 020724/0298 →