Flat display and method for modulating a clock signal for driving the same
View Patent ↗A flat display and a method for modulating a clock signal for driving a flat display are provided. The flat display includes a clock generator and a clock modulator. The clock generator provides a clock signal that includes at least a first cycle waveform and a second cycle waveform following said first cycle waveform. The first cycle waveform is modulated by the clock modulator as a first modulated cycle waveform divided by a first positive modulated cycle waveform and a first negative modulated cycle waveform, and the second cycle waveform is modulated as a second modulated cycle waveform divided by a second positive modulated cycle waveform and a second negative modulated cycle waveform. The first positive modulated cycle waveform and the first negative modulated cycle waveform have a first duration difference, and the second positive modulated cycle waveform and the second negative modulated cycle waveform have a second duration difference different from the first duration difference.
1. A flat display, comprising:
a clock generator providing a clock signal, said clock signal comprising at least a first cycle waveform and a second cycle waveform immediately following said first cycle waveform; and
a clock modulator modulating said clock signal, wherein said first cycle waveform is modulated as a first modulated cycle waveform made up of a first positive modulated cycle waveform and a first negative modulated cycle waveform, and said second cycle waveform is modulated as a second modulated cycle waveform made up of a second positive modulated cycle waveform and a second negative modulated cycle waveform, and durations of said first modulated cycle waveform, said second modulated cycle waveform, said first cycle waveform and said second cycle waveform are equal,
wherein said first positive modulated cycle waveform and said first negative modulated cycle waveform within same said first modulated cycle waveform have a first duration difference, and said second positive modulated cycle waveform and said second negative modulated cycle waveform within same said second modulated cycle waveform have a second duration difference different from said first duration difference.
2. The flat display according to claim 1 , wherein said clock signal is originally generated according to an audible frequency, and said clock signal is modulated by said clock modulator to generate other frequency that is not audible.
3. The flat display according to claim 1 , wherein a first duration ratio of a first positive modulated cycle waveform to said first modulated cycle waveform and a second duration ratio of a second positive modulated cycle waveform to said second modulated cycle waveform are in a range of 20%-80%.
4. The flat display according to claim 1 , wherein said clock signal further comprises a third cycle waveform following said second cycle waveform;
wherein said third cycle waveform is modulated by said clock modulator to as a third modulated cycle waveform divided by a third positive modulated cycle waveform and a third negative modulated cycle waveform, and said third positive modulated cycle waveform and said third negative modulated cycle waveform have a third duration difference different from said second duration difference.
5. The flat display according to claim 4 , wherein said third duration difference is equal to said first duration difference.
6. The flat display according to claim 4 , wherein the absolute value of said third duration difference is equal to the absolute value of said first duration difference.
7. The flat display according to claim 4 , wherein said second duration difference is the median of said first duration difference and said third duration difference.
8. The flat display according to claim 4 , wherein the durations of said first modulated cycle waveform, said second modulated cycle waveform, and said third modulated cycle waveform are equal.
9. The flat display according to claim 4 , wherein a first duration ratio of a first positive modulated cycle waveform to said first modulated cycle waveform, a second duration ratio of a second positive modulated cycle waveform to said second modulated cycle waveform, a third duration ratio of a third positive modulated cycle waveform to said third modulated cycle waveform are in a range of 20%-80%.
10. The flat display according to claim 1 , further comprising:
an ASIC, wherein said clock generator and said clock modulator are embedded in said ASIC;
a charge pump; and
a panel:
wherein said ASIC receives the voltage signals provided by said charge pump and then send it to said panel for providing a common voltage source.
11. A method for modulating a clock signal for driving a flat display, said flat display having a clock generator and a clock modulator, said method comprising:
providing said clock signal by said clock generator, wherein said clock signal comprises at least a first cycle waveform and a second cycle waveform immediately following said first cycle waveform; and
modulating said clock signal by said clock modulator, comprising:
modulating said first cycle waveform as a first modulated cycle waveform made up of a first positive modulated cycle waveform and a first negative modulated cycle waveform; and
modulating said second cycle waveform as a second modulated cycle waveform by made up of a second positive modulated cycle waveform and a second negative modulated cycle waveform and said second positive modulated cycle waveform and said second negative modulated cycle waveform, wherein durations of said first modulated cycle waveform, said second modulated cycle waveform, said first cycle waveform and said second cycle waveform are equal,
wherein said first positive modulated cycle waveform and said first negative modulated cycle waveform within same said first modulated cycle waveform have a first duration difference, and said second positive modulated cycle waveform and said second negative modulated cycle waveform within same said second modulated cycle waveform have a second duration difference different from said first duration difference.
12. The method according to claim 11 , wherein said clock signal is originally generated according to an audible frequency, and said clock signal is modulated by said clock modulator to generate other frequency that is not audible.
13. The method according to claim 11 , wherein a first duration ratio of a first positive modulated cycle waveform to said first modulated cycle waveform and a second duration ratio of a second positive modulated cycle waveform to said second modulated cycle waveform are in a range of 20%-80%.
14. The method according to claim 11 , wherein said clock signal further comprises a third cycle waveform following said second cycle waveform;
wherein the step of modulating said clock signal comprises modulating said third cycle waveform as a third modulated cycle waveform divided by a third positive modulated cycle waveform and a third negative modulated cycle waveform, and said third positive modulated cycle waveform and said third negative modulated cycle waveform have a third duration difference different from said second duration difference.
15. The method according to claim 14 , wherein said third duration difference is equal to said first duration difference.
16. The method according to claim 14 , wherein the absolute value of said third duration difference is equal to the absolute value of said first duration difference.
17. The method according to claim 14 , wherein said second duration difference is the median of said first duration difference and said third duration difference.
18. The flat display according to claim 1 , wherein said clock signal comprises a series of waverform sets, wherein each of said waveform sets comprises said first cycle waveform and said second cycle waveform.
19. The method according to claim 11 , wherein said clock signal comprises a series of waverform sets, wherein each of said waveform sets comprises said first cycle waveform and said second cycle waveform.
20. A flat display, comprising:
a clock generator providing a clock signal, said clock signal comprising a series of waveform sets, wherein each of said waveform sets comprises at least a first cycle waveform and a second cycle waveform following successively said first cycle waveform; and
a clock modulator modulating said clock signal, wherein each of said first cycle waveforms is modulated as a first modulated cycle waveform made up of a first positive modulated cycle waveform and a first negative modulated cycle waveform, and each of said second cycle waveforms is modulated as a second modulated cycle waveform made up of a second positive modulated cycle waveform and a second negative modulated cycle waveform, and durations of said first modulated cycle waveforms, said second modulated cycle waveforms, said first cycle waveforms and said second cycle waveforms are equal,
wherein said first positive modulated cycle waveform of each of said first modulated cycle waveforms and said first negative modulated cycle waveform of each of corresponding same first modulated cycle waveform have a first duration difference, and said second positive modulated cycle waveform of each of said second modulated cycle waveforms and said second negative modulated cycle waveform of each of corresponding same second modulated cycle waveform have a second duration difference different from said first duration difference.