Method for frequency compensation in timing recovery
A method of digitally controlling a timing recovery loop to control jitter and reduce word-length in a recovered clock is provided. A timing error detector provides an output identifying the error sign. First and second randomizing digital attenuators provide first and second estimates of the phase error in a timing signal. A controller receives the first estimate and provides a signal to an NCO. An output from the NCO provides feedback to the error detector to complete a first order feedback loop, providing a first estimate phase error compensation. An integrator receives the second estimate and provides an output estimate for frequency offset of the timing signal that is received by the controller and the sign and magnitude of the integrated phase error are calibrated to provide a frequency offset. The controller determines a number of additional updates to the NCO required to minimize jitter and reduce word-length.
1. A method of adjusting an output signal generated by an oscillator, the method comprising:
detecting a timing difference between an incoming signal and the output signal generated by the oscillator;
generating a first signal using a first randomizing digital signal attenuator, wherein the first signal is based, at least in part, on the timing difference, and wherein said generating a first signal includes providing an indication of the sign of the timing difference to the first randomizing digital attenuator;
generating a second signal using a second randomizing digital attenuator, wherein the second signal is based, at least in part, on the timing difference, and wherein said generating a second signal includes providing an indication of the sign of the timing difference to the second randomizing digital attenuator;
integrating the second signal to generate an integrated signal; and
generating control signals for the oscillator based, at least in part, on the first signal and the integrated signal.
2. The method of claim 1 , wherein the second signal is different from the first signal.
3. The method of claim 1 , wherein said detecting a timing difference comprises detecting a sign of the timing difference.
4. The method of claim 3 , wherein said generating a first signal comprises generating the first signal based on the sign of the timing difference.
5. The method of claim 1 , wherein the indication of the sign of the timing difference is less than eight bits in length.
6. The method of claim 1 , wherein the indication of the sign of the timing difference is two bits in length.
7. The method of claim 1 , wherein the second signal is based, at least in part, on the timing difference at a first time, and wherein said integrating the second signal comprises:
delaying the second signal to generate a delay signal;
generating a new second signal based, at least in part, on a timing difference between the input signal and the output signal at a second time; and
adding the delay signal and the new second signal.
8. The method of claim 1 , wherein the oscillator comprises a numerically controlled oscillator, and wherein the control signals comprise increment or decrement pulses.
9. The method of claim 1 , wherein the first signal is indicative of a phase difference between the input signal and the output signal, and wherein the integrated signal is indicative of a frequency offset between the input signal and the output signal.
10. A timing recovery loop comprising:
an error detector configured to generate an instantaneous error signal indicative of a timing difference between an input signal and a feedback signal;
a first randomizing digital attenuator configured to receive the instantaneous error signal and generate a first randomized digital signal based, at least in part, on the instantaneous error signal;
a second randomizing digital attenuator configured to receive the instantaneous error signal and generate a second randomized digital signal based, at least in part, on the instantaneous error signal;
an integrator configured to receive the second randomized digital signal and generate an integrated signal based, at least in part, on an integral of the second randomized digital signal;
a controller configured to receive the instantaneous error signal and the integrated signal, wherein the controller is further configured to generate oscillator control signals based, at least in part, on the instantaneous error signal and the integrated signal; and
an oscillator configured to receive the oscillator control signals and generate the feedback signal based, at least in part, on the oscillator control signals.
11. The timing recovery loop of claim 10 , wherein the error detector comprises a sign interpreter, and wherein the instantaneous error signal is indicative of a sign of the timing difference between the input signal and the feedback signal.
12. The timing recovery loop of claim 11 , wherein the instantaneous error signal is less than eight bits in length.
13. The timing recovery loop of claim 11 , wherein the instantaneous error signal is two bits in length.
14. The timing recovery loop of claim 10 , wherein the oscillator control signals are configured to reduce the timing difference between the input signal and the feedback signal.
15. The timing recovery loop of claim 10 , wherein the oscillator control signals comprise a plurality of pulses, and wherein the controller is further configured to generate the pulses as either a random or quasi-periodic sequence.
16. The timing recovery loop of claim 10 , wherein the integrator comprises a delay element configured to delay the instantaneous error signal and a summer configured to combine the delayed instantaneous error signal with a subsequent instance of the instantaneous error signal.
17. A receiver comprising:
an input terminal configured to receive an input signal transmitted in accordance with a first clock signal;
an oscillator configured to generate a second clock signal; and
a timing recovery loop configured to compensate for a timing difference between the first clock signal and the second clock signal, wherein the timing recovery loop includes:
an error detector configured to generate an instantaneous error signal indicative of the timing difference between the first clock signal and the second clock signal;
a first randomizing digital attenuator configured to receive the instantaneous error signal and generate a first randomized digital signal based, at least in part, on the instantaneous error signal;
a second randomizing digital attenuator configured to receive the instantaneous error signal and generate a second randomized digital signal based, at least in part, on the instantaneous error signal;
an integrator configured to receive the second randomized digital signal and generate an integrated signal based, at least in part, on an integral of the second randomized digital signal; and
a controller configured to receive the instantaneous error signal and the integrated signal, wherein the controller is further configured to generate oscillator control signals based, at least in part, on the instantaneous error signal and the integrated signal;
wherein the oscillator is further configured to adjust a phase, a frequency, or both of the second clock signal based, at least in part, on the oscillator control signals.
18. The receiver of claim 17 , wherein the error detector comprises a sign interpreter, and wherein the instantaneous error signal is indicative of a sign of the timing difference between the first and second clock signals.
19. The receiver of claim 18 , wherein the instantaneous error signal is less than eight bits in length.
20. The receiver of claim 18 , wherein the instantaneous error signal is two bits in length.
21. The receiver of claim 17 , wherein the oscillator control signals comprise a plurality of pulses, and wherein the controller is further configured to generate the pulses as either a random or quasi-periodic sequence.
22. The receiver of claim 17 , wherein the integrator comprises a delay element configured to delay the instantaneous error signal and a summer configured to combine the delayed instantaneous error signal with a subsequent instance of the instantaneous error signal.