IP Library Granted Patent US 7,532,519
Granted Patent B2
US 7,532,519 · App. 12/007,298 · Granted May 12, 2009

Semiconductor memory device

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Quick Facts
Patent No.
US 7,532,519
App. No.
12/007,298
Granted
May 12, 2009
Kind
B2
Abstract

A semiconductor memory device which is highly reliable, is operable at a low voltage and a high speed, and is produced at a high production yield is provided. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied comprises a plurality of memory cells each including a plurality of local charge portions each capable of storing a static charge corresponding to the data. Either two of the local charge portions store the charges in a complementary state.

Claims (11)

1. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied, the semiconductor memory device comprising:

a plurality of memory cells each including a plurality of local charge portions each capable of storing a static charge corresponding to the data;

wherein either two of the local charge portions store the charges in a complimentary state, and

the semiconductor memory device further comprises a reference cell connected to a bit line for reading the charges stored in the complementary state via a switch.

2. A semiconductor memory device according to claim 1 , wherein the reference cell is used for erasure verification.

3. A semiconductor memory device according to claim 1 , wherein the reference cell is used for write verification.

4. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied, the semiconductor memory device comprising:

a plurality of memory cells each including a plurality of local charge portions each capable of storing a static charge corresponding to the data;

wherein either two of the local charge portions store the charges in a complimentary state,

the two local charge portions are included in different memory cells connected to different word lines, and

write verification is performed by applying different charges to the different word lines, respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →