Method of fabricating a probe card
View Patent ↗A probe card for testing dice on a wafer includes a substrate, a number of cantilevers formed on a surface thereof, and a number of probes extending from unsupported ends of the cantilevers. The unsupported ends of the cantilevers project over cavities on the surface of the substrate. The probes have tips to contact pads on the dice under test. The probe card may include a compressive layer above the surface of the substrate with a number of holes through which the probes extend.
1. A method of fabricating a probe card, the method comprising:
forming a plurality of electrically conducting cantilevers on a surface of a substrate, each of the cantilevers having an unsupported end projecting over one of an equal number of cavities formed on the surface of the substrate;
forming a plurality of electrically conducting probes extending from the unsupported ends of the cantilevers, each of the probes having a tip for contacting a pad on a surface of a device under test (DUT); and
forming an electrically insulating compressive layer above the surface of the substrate, the compressive layer having a plurality of holes extending therethrough and through which the probes extend to contact pads on the surface of the DUT.
2. The method of claim 1 , wherein the compressive layer is formed to a thickness equal to or less than about 300 microns.
3. The method of claim 1 wherein the compressive layer comprises polyimide and a nitride capping layer.
4. The method of claim 1 wherein each of the probes comprises a body made of a first material and having a first cross-sectional area, and a tip made of a second material and having a second cross-sectional area, and wherein the second cross-sectional area is smaller than the first cross-sectional area.
5. The method of claim 1 wherein the substrate comprises an anti-wafer having a plurality of electrically conducting wirings formed thereon for electrically coupling the probes through the electrically conductive cantilevers to a test circuit.
6. The method of claim 5 wherein the test circuit is formed in the anti-wafer.
7. The method of claim 5 wherein the substrate further comprises a gasket abutting a backside surface of the anti-wafer to increase co-planarity between the surface of the substrate and the surface of the DUT.
8. The method of claim 5 wherein the anti-wafer is divided into a plurality of probe dice, and wherein each of the probe die comprises at least one conducting cantilever projecting over a cavity formed on the surface of the probe die, and an electrically conducting probe extending from the unsupported end of the cantilever to contact a pad on a surface of a DUT on the wafer.
9. The method of claim 8 wherein the plurality of probe dice are separated from one another by a plurality of intersecting recesses, and wherein wirings to the anti-wafer are formed in the plurality of intersecting recesses to prevent scratching the wafer.