Disk array apparatus
View Patent ↗A disk array apparatus where, when a failure occurs at a part of a cache memory, a memory area of an I/O processing controller other than the memory area where the failure has occurred is utilized without taking over the whole I/O processing to an I/O processing controller of other system is provided, so that influence of performance degradation can be minimized. In a disk array apparatus including dual cache memories, when a failure occurs at a part of the cache memory, only a memory area where the failure has occurred is closed, and reallocation thereof to another memory area of the same cache memory is conducted to continue an I/O processing.
1. A disk array apparatus comprising:
a plurality of I/O processing controllers for controlling an I/O processing between the I/O processing controller and an upper apparatus; and a storage apparatus storing data obtained according to I/O processings conduced in the plurality of I/O processing controllers,
wherein each of the plurality of I/O processing controllers includes: a processor for performing an I/O processing; and a cache memory temporarily storing data obtained according to the I/O processing at the processor;
the cache memory is logically divided to a plurality of memory area; and
the storage apparatus includes a plurality of logical units, and the divided memory areas are allocated to respective logical units,
when a failure occurs at a part of the cache memory, the processor performs:
identification of an address of the cache memory where the failure has occurred and closes a first memory area of the identified address;
determination about an access state from the upper apparatus to reallocate the logical unit that has been allocated to the first memory area to a second memory area of the cache memory where the failure has occurred based on the result of the determination; and
continuation of an I/O processing from the upper apparatus using the reallocated second memory area.
2. The disk array apparatus according to claim 1 ,
wherein, as the access state from the upper apparatus, presence/absence of a redundant path configuration between the upper apparatus and the I/O processing controller having the cache memory where the failure has occurred is determined, and according to the determination, when the redundant path configuration is absent, a usage rate of each memory area of the cache memory where the failure has occurred is checked, and reallocation to a memory area whose usage rate is low according to the result of the check is performed to continue the I/O processing.
3. The disk array apparatus according to claim 2 ,
wherein, when the redundant path configuration is present according to the result of the determination, switching to a cache memory of other I/O processing controller other than the I/O processing controller having the cache memory where the failure has occurred is performed to continue the I/O processing.
4. The disk array apparatus according to claim 1 ,
wherein, as the access state from the upper apparatus, a load state of other I/O processing controller other than the I/O processing controller having the cache memory where the failure has occurred is determined, and when the load is high according to the result of the determination, a usage rate of each memory area of the cache memory where the failure has occurred is checked, and reallocation to a memory area whose usage rate is low according to the result of the check is performed to continue the I/O processing.
5. The disk array apparatus according to claim 4 ,
wherein, when the load is not high according to the result of the determination, switching to a cache memory of other I/O processing controller other than the I/O processing controller having the cache memory where the failure has occurred is performed to continue the I/O processing.
6. The disk array apparatus according to claim 1 ,
wherein, as the access state from the upper apparatus, presence/absence of a redundant path configuration between the upper apparatus and the I/O processing controller having the cache memory where the failure has occurred and a load state of other I/O processing controller other than the I/O processing controller having the cache memory where the failure has occurred are determined, and when the redundant path is absent and the load is high according to the result of the determination, a usage rate of each memory area of the cache memory where the failure has occurred is checked, and reallocation to a memory area whose usage rate is low according to the result of the check is performed to continue the I/O processing.
7. The disk array apparatus according to claim 6 ,
wherein, when the redundant path is absent and the load is not high according to the result of the determination, a usage rate of each memory area of the cache memory where the failure has occurred is checked, and reallocation to a memory area whose usage rate is low according to the result of the check is performed to continue the I/O processing.
8. The disk array apparatus according to claim 6 ,
wherein, when the redundant path is present and the load is high according to the result of the determination, a usage rate of each memory area of the cache memory where the failure has occurred is checked, and reallocation to a memory area whose usage rate is low according to the result of the check is performed to continue the I/O processing.
9. The disk array apparatus according to claim 6 ,
wherein, when the redundant path is present and the load is not high according to the result of the determination, switching to a cache memory of other I/O processing controller other than the I/O processing controller having the cache memory where the failure has occurred is performed to continue the I/O processing.
10. A disk array apparatus comprising:
a plurality of I/O processing controllers for controlling an I/O processing between the I/O processing controller and an upper apparatus; and a storage apparatus storing data obtained according to I/O processings conduced in the plurality of I/O processing controllers,
wherein each of the plurality of I/O processing controllers includes: a processor for performing an I/O processing; and a cache memory temporarily storing data obtained according to the I/O processing at the processor;
the cache memory is logically divided to a plurality of memory area; and
the storage apparatus includes a plurality of logical units, and the divided memory areas are allocated to respective logical units,
when a failure occurs at a part of the cache memory, the processor performs:
identification of an address of the cache memory where the failure has occurred and closes a first memory area of the identified address;
determination about an access state from the upper apparatus to reallocate the logical unit that has been allocated to the first memory area to a second memory area of the cache memory where the failure has occurred based on the result of the determination; and
continuation of an I/O processing from the upper apparatus using the reallocated second memory area,
wherein, as the access state from the upper apparatus, presence/absence of a redundant path configuration between the upper apparatus and the I/O processing controller having the cache memory where the failure has occurred and a load state of other I/O processing controller other than the I/O processing controller having the cache memory where the failure has occurred are determined, and when the redundant path is absent and the load is high according to the result of the determination, a usage rate of each memory area of the cache memory where the failure has occurred is checked, and reallocation to a memory area whose usage rate is low according to the result of the check is performed to continue the I/O processing, and when the redundant path is present and the load is not high according to the result of the determination, switching to a cache memory of other I/O processing controller other than the I/O processing controller having the cache memory where the failure has occurred is performed to continue the I/O processing.