Semiconductor device and semiconductor substrate
View Patent ↗In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.
1. A method of manufacturing a semiconductor device having p-MOS and n-MOS transistors, the method comprising:
(a) forming a Si 1-x Ge x strain applying layer, which is substantially strain relaxed and has an in-plane lattice constant larger than that of unstrained Si within a range of proportions greater than 0% and less than 4% on a semiconductor substrate, where 0<x<1;
(b) growing a strained Si layer on said Si 1-x Ge x strain applying layer, thereby forming said strained Si layer which is subjected to in-plane tensile strain;
(c) forming a SiO 2 layer on a surface of said strained Si layer;
(d) bonding said SiO 2 layer and a supporting substrate to each other;
(e) removing said semiconductor substrate, said Si 1-x Ge x strain applying layer and a part of said strained Si layer, thereby forming an SOI substrate composed of a stack of said supporting substrate, said SiO layer and said strained Si layer; and
(f) forming said p-MOS and n-MOS transistor on a surface of said strained Si layer.
2. A method of manufacturing a semiconductor device according to claim 1 , wherein an in-plane lattice constant of said strained Si layer is larger than that of unstrained Si within a range of proportions greater than 0% and less than 4%.
3. A method of manufacturing a semiconductor device according to claim 1 , wherein the surface orientation of each of said Si 1-x Ge x strain applying layer and said strained Si layer is {110}.
4. A method of manufacturing a semiconductor device according to claim 1 , wherein channel region of said p-MOS and n-MOS transistors are formed where an in-plane lattice constant of said strained Si layer is larger than that of unstrained Si within a range of proportions greater than 0% and less than 4%.
5. A method of manufacturing a semiconductor device according to claim 1 , wherein the surface orientation of each of said Si 1-x Ge x strain applying layer and said strained Si layer is {100}.
6. A method of manufacturing a semiconductor device according to claim 1 , wherein the surface orientation of each of said Si 1-x Ge x strain applying layer and said strained Si layer is {110}.
7. A method of manufacturing a semiconductor device according to claim 1 , wherein, in the step of (c), subjecting a surface of said strained Si layer to thermal oxidation.