Liquid crystal display device including driving circuit and method of fabricating the same
View Patent ↗A method of fabricating an array substrate structure for a liquid crystal display device includes defining a display area and a non-display area on a substrate, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and a p-type driving TFT portion; forming a first gate electrode in the display area, a second and a third gate electrodes and a first capacitor electrode in the non-display area; an amorphous silicon layer on the substrate; crystallizing the amorphous silicon layer to a polycrystalline silicon layer and doping specific portions of the polycrystalline silicon layer with plurality of impurity concentrations; and forming a first semiconductor layer in the display area, a second and a third semiconductor layers and a second capacitor electrode in the non-display area.
1. An array substrate structure for a liquid crystal display device, comprising:
first, second and third gate electrodes on a substrate having a display area and a non-display area, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and a p-type driving TFT portion, the first gate electrode disposed in the pixel TFT portion, the second gate electrode disposed in the n-type driving TFT portion, the third gate electrode disposed in the p-type driving TFT portion;
a gate line in the display area on the substrate;
a pixel electrode in the pixel electrode area on the substrate;
a gate insulating layer on the first, second, and third gate electrodes, the gate line, and the pixel electrode;
first, second and third semiconductor layers of polycrystalline silicon on the gate insulating layer, the first semiconductor layer disposed in the pixel TFT portion, the second semiconductor layer disposed in the n-type driving TFT portion, and the third semiconductor layer disposed in the p-type driving TFT portion;
a passivation pattern on the first, second and third semiconductor layers, the passivation pattern exposing side portions of each of the first, second and third semiconductor layers;
first source and drain electrodes, second source and drain electrodes, and third source and drain electrodes on the substrate, the first source and drain electrodes contacting the side portions of the first semiconductor layer, the second source and drain electrodes contacting the side portions of the second semiconductor layer, the third source and drain electrodes contacting the side portions of the third semiconductor layer; and
a data line crossing the gate line and connected to the first source electrode.
2. The substrate structure according to claim 1 , wherein the first, second and third gate electrodes and the pixel electrode include a single layer of a transparent conductive material.
3. The substrate structure according to claim 1 , wherein the gate line includes a double layer of a transparent conductive material and a metallic material.
4. The substrate structure according to claim 1 , further comprising a first capacitor electrode connected to the pixel electrode and a second capacitor electrode over the first capacitor electrode.
5. The substrate structure according to claim 4 , wherein the first capacitor electrode includes a transparent conductive material, and wherein the second capacitor electrode includes the polycrystalline silicon material.
6. The substrate structure according to claim 1 , wherein the first drain electrode directly contacts the pixel electrode.
7. The substrate structure according to claim 1 , wherein the gate insulating layer and the passivation pattern have an island shape.