Nanoscale interconnection interface
View Patent ↗One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2 k or fewer nanowires, employing supplemental, internal address lines to map 2 k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2 k nanowires, with n>k, using 2 k , well-distributed, n-bit external addresses to access the 2 k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.
1. A method that evaluates a mapping of k-bit nanowire numbers to n-bit internal addresses carried by n internal address signal lines of a demultiplexer, the method comprising:
computing an evaluation metric for the mapping; and
comparing the computed evaluation metric to an evaluation metric computed for a different mapping to produce a mapping evaluation.
2. The method of claim 1 wherein the evaluation metric includes a splay metric which favors mappings with large minimal Hamming distances between n-bit internal addresses and narrow distributions of distances between n-bit internal addresses.
3. The method of claim 2 wherein the splay metric S is expressed as:
S
=
d
max
-
d
min
d
max
wherein d max is the maximum Hamming distance between two n-bit addresses,
d min is the minimum Hamming distance between two n-bit internal addresses; and
a smaller the value of S indicates a more desirable the mapping.
4. The method of claim 1 wherein the evaluation metric includes an efficiency metric which favors mappings with a minimal number n of internal address signal lines.
5. The method of claim 4 wherein the efficiency metric R is expressed as:
R
=
k
n
.
_
6. A computer readable storage medium that encodes computer instructions that implement the method of claim 1 .
7. A method for designing a demultiplexer, the method comprising:
selecting a number of mappings of k-bit nanowire numbers to n-bit internal addresses carried by n internal address signal lines of the demultiplexer;
computing an evaluation metric for each of the number of mappings; and
comparing the computed evaluation metrics to select a mapping for implementation by the demultiplexer.
8. The method of claim 7 wherein the evaluation metric includes a splay metric which favors mappings with large minimal Hamming distances between n-bit internal addresses and narrow distributions of distances between n-bit internal addresses.
9. The method of claim 8 wherein the splay metric S is expressed as:
S
=
d
max
-
d
min
d
max
wherein d max is the maximum Hamming distance between two n-bit addresses,
d min is the minimum Hamming distance between two n-bit internal addresses; and
a smaller the value of S indicates a more desirable the mapping.
10. The method of claim 7 wherein the evaluation metric includes an efficiency metric which favors mappings with a minimal number n of internal address signal lines.
11. The method of claim 10 wherein the efficiency metric R is expressed as:
R
=
k
n
.
12. A computer readable storage medium that encodes computer instructions that implement the method of claim 7 .