Shift register with lower power consumption and liquid crystal display using the same
View Patent ↗An exemplary shift register ( 20 ) includes a plurality of shift register units ( 200 ) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an input terminal (VIN), a first output terminal (VOUT 1 ), a second output terminal (VOUT 2 ), a first common node (P 1 ), a second common node (P 2 ), a first switch circuit ( 31 ), a second switch circuit ( 32 ), a third switch circuit ( 33 ), a fourth switch circuit ( 34 ), a fifth switch circuit ( 35 ), a six switch circuit ( 36 ), a nor gate, an inverter, and an and gate.
1. A shift register, comprising a plurality of shift register units, each shift register unit comprising:
a nor gate comprising a first input terminal connected to an input terminal of the shift register unit, a second input terminal connected to a first output terminal of the shift register unit, and an output terminal;
an and gate comprising a first input terminal connected to the input terminal, a second input terminal connected to the first output terminal, and an output terminal connected to a second output terminal of the shift register unit;
a first switch circuit controlled by the output terminal of the nor gate and configured for providing a clock signal to a first common node of the shift register unit;
a second switch circuit controlled by the output terminal of the nor gate and configured for providing a low level signal to the first common node;
a third switch circuit controlled by the input terminal and the first common node and configured for providing a high level signal to a second common node of the shift register unit;
a fourth switch circuit controlled by the first output terminal and the first common node and configured for providing a high level signal to the second common node;
a fifth switch circuit controlled by the first common node and the first output terminal and configured for providing a low level signal to the second common node;
a sixth switch circuit controlled by the first common node and the input terminal and configured for providing a low level signal to the second common node; and
an inverter connected between the second common node and the first output terminal.
2. The shift register as claimed in claim 1 , further comprising a clock signal input terminal configured for receiving the clock signal, a high level signal input terminal configured for receiving the high level signal, and a low level signal input terminal configured for receiving the low level signal.
3. The shift register as claimed in claim 2 , wherein the first switch circuit is a transistor, a gate electrode of the transistor is connected to the output terminal of the nor gate, a source electrode of the transistor is connected to the clock signal input terminal, a drain electrode of the transistor is connected to the first common node.
4. The shift register as claimed in claim 3 , wherein the transistor is a P-channel metal-oxide-semiconductor transistor.
5. The shift register as claimed in claim 2 , wherein the second switch circuit is a transistor, a gate electrode of the transistor is connected to the output terminal of the nor gate, a source electrode of the transistor is connected to the low level signal input terminal, a drain electrode of the transistor is connected to the first common node.
6. The shift register as claimed in claim 5 , wherein the transistor is an N-channel metal-oxide-semiconductor transistor.
7. The shift register as claimed in claim 2 , wherein the third switch circuit comprises a first transistor and a second transistor, a gate electrode of the first transistor is connected to the input terminal, a source electrode of the first transistor is connected to the high level signal input terminal, a drain electrode of the first transistor is connected to a drain electrode of the second transistor, a gate electrode of the second transistor is connected to the first common node, a source electrode of the second transistor is connected to the second common node.
8. The shift register as claimed in claim 7 , wherein the first transistor is a P-channel metal-oxide-semiconductor transistor, and the second transistor is an N-channel metal-oxide-semiconductor transistor.
9. The shift register as claimed in claim 8 , further comprising a second inverter wherein the second inverter is connected between the first common node and the gate electrode of the second transistor.
10. The shift register as claimed in claim 9 , wherein the first transistor and the second transistor are P-channel metal-oxide-semiconductor transistors.
11. The shift register as claimed in claim 2 , wherein the fourth switch circuit comprises a first transistor and a second transistor, a gate electrode of the first transistor is connected to the first common node, a source electrode of the first transistor is connected to the high level signal input terminal, a drain electrode of the first transistor is connected to a source electrode of the second transistor, a gate electrode of the second transistor is connected to the first output terminal, a drain electrode of the second transistor is connected to the second common node.
12. The shift register as claimed in claim 11 , wherein the first transistor and the second transistor are P-channel metal-oxide-semiconductor transistors.
13. The shift register as claimed in claim 2 , wherein the fifth switch circuit comprises a first transistor and a second transistor, a gate electrode of the first transistor is connected to the first output terminal, a drain electrode of the first transistor is connected to the second common node, a source electrode of the first transistor is connected to a source electrode of the second transistor, a gate electrode of the second transistor is connected to the first common node, a drain electrode of the second transistor is connected to the low level signal input terminal.
14. The shift register as claimed in claim 13 , wherein the first transistor is an N-channel metal-oxide-semiconductor transistor, and the second transistor is a P-channel metal-oxide-semiconductor transistor.
15. The shift register as claimed in claim 13 , further comprising a second inverter, wherein the second inverter is connected between the first common node and the gate electrode of the second transistor.
16. The shift register as claimed in claim 15 , wherein the first transistor and the second transistor are N-channel metal-oxide-semiconductor transistors.
17. The shift register as claimed in claim 2 , wherein the sixth switch circuit comprises a first transistor and a second transistor, a gate electrode of the first transistor is connected to the first common node, a drain electrode of the first transistor is connected to the second common node, a source electrode of the first transistor is connected to a drain electrode of the second transistor, a gate electrode of the second transistor is connected to the input terminal, a source electrode of the second transistor is connected to the low level signal input terminal.
18. The shift register as claimed in claim 17 , wherein the first transistor and the second transistor are N-channel metal-oxide-semiconductor transistors.
19. A shift register, comprising a plurality of shift register units connected one by one, each of the shift register units comprising a clock signal input terminal configured for receiving a clock signal, a high level signal input terminal configured for receiving a high level signal, a low level signal input terminal configured for receiving a low level signal, an input terminal configured for receiving an input signal, a first output terminal configured for outputting a first output signal, and a second output terminal configured for outputting a second output signal;
wherein the second output signal is low level when the clock signal is low level, the input signal is high level, and the first output signal is low level;
the second output signal is high level when the clock signal is high level, the input signal is high level, and the first output signal is high level;
the second output signal is low level when the clock signal is low level, the input signal is low level, and the first output signal is high level;
the second output signal is low level when the clock signal is high level, the input signal is low level, and the first output signal is low level; and
the second output signal is low level when the clock signal is low level, the input signal is low level, and the first output signal is low level.
20. A liquid crystal display, comprising a liquid crystal panel and a driver circuit configured for driving the liquid crystal panel; the driver circuit comprising a shift register; the shift register comprising a plurality of shift register units, each shift register unit comprising:
a nor gate comprising a first input terminal connected to an input terminal of the shift register unit, a second input terminal connected to a first output terminal of the shift register unit, and an output terminal;
an and gate comprising a first input terminal connected to the input terminal, a second input terminal connected to the first output terminal, and an output terminal connected to a second output terminal of the shift register unit;
a first switch circuit controlled by the output terminal of the nor gate and configured for providing a clock signal to a first common node of the shift register unit;
a second switch circuit controlled by the output terminal of the nor gate and configured for providing a low level signal to the first common node;
a third switch circuit controlled by the input terminal and the first common node and configured for providing a high level signal to a second common node of the shift register unit;
a fourth switch circuit controlled by the first output terminal and the first common node and configured for providing a high level signal to the second common node;
a fifth switch circuit controlled by the first common node and the first output terminal and configured for providing a low level signal to the second common node;
a sixth switch circuit controlled by the first common node and the input terminal and configured for providing a low level signal to the second common node; and
an inverter connected between the second common node and the first output terminal.