Multilayer passive circuit topology

1. A multilayer circuit comprising:

a multilayer inductor comprising;

a first set of parallel conductive traces formed on a first layer;

a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and

a plurality of vias that connect respective parallel conductive traces from the first and second layers to form inductor windings; and

a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.

2. The circuit of claim 1 , wherein the different layers comprise a third layer and a fourth layer, and further comprising a dielectric layer disposed between the third and fourth layers.

3. The circuit of claim 1 , further comprising a dielectric layer disposed between the first and second layers.

4. The circuit of claim 1 , further comprising a ground layer disposed between the multilayer inductor and multilayer capacitor to isolate the multilayer inductor from the multilayer capacitor.

5. The circuit of claim 1 , further comprising a first input/output via coupled to an end of the multilayer inductor and a second input/output via coupled to an end of the multilayer capacitor.

6. The circuit of claim 1 , further comprising a plurality of multilayer inductors and a plurality multilayer capacitors affanged in a circuit.

7. The circuit of claim 6 , wherein the plurality of multilayer inductors and plurality of multilayer capacitors are arranged as a plurality of inductor-capacitor circuits interconnected with one another to form a multi-pole filter.

8. The circuit of claim 7 , further comprising a plurality of tuning capacitors coupled on opposing ends of each of the plurality of multilayer inductors.

9. The circuit of claim 8 , further comprising a plurality of sets of a plurality of space apart parallel vias arranged to form faraday cages to surround and isolate each of the multilayer inductor and associated tuning capacitors.

10. The circuit of claim 1 , further comprising a resistive element coupled to at least one of the multilayer inductor and multilayer capacitor.

11. A multilayer circuit comprising:

a plurality of multilayer inductors, each multilayer inductor being formed from a first set of parallel conductive traces and a second set of parallel conductive traces formed on different spaced apart layers and a plurality of vias that connect respective parallel conductive traces from the different layers to form inductor windings; and

a plurality of multilayer capacitors, each multilayer capacitor being formed from a first conductive plate and a second conductive plate formed on different layers wherein the plurality of multilayer inductors and the plurality multilayer capacitors are arranged in a circuit.

12. The circuit of claim 11 , further comprising a dielectric layer disposed between the different layers of each of the multilayer inductor and multilayer capacitor.

13. The circuit of claim 11 , wherein the plurality of multilayer inductors and plurality of multilayer capacitors are arranged as a plurality of inductor-capacitor circuits interconnected with one another to form a multi-pole filter.

14. The circuit of claim 13 , further comprising a plurality of tuning capacitors coupled on opposing ends of each of the plurality of multilayer inductors.

15. The circuit of claim 14 , further comprising a plurality of sets of a plurality of space apart parallel vias arranged to form faraday cages to surround and isolate each of the multilayer inductors and associated tuning capacitors.

16. A method of fabricating a multilayer circuit, the method comprising:

forming a first set of parallel conductive traces on a first layer;

forming a second set of parallel conductive traces on a second layer spaced apart from the first layer;

forming a plurality of vias that connect respective parallel conductive traces from the first and second layers to form a multilayer inductor;

forming a first conductive plate on a third layer;

forming a second conductive plate on a fourth layer being spaced apart from third layer to form a multilayer capacitor; and

forming a coupling via that connects the multilayer inductor to the multilayer capacitor.

17. The method of claim 16 , wherein the forming a first set of parallel conductive traces on a first layer, the forming a second set of parallel conductive traces on a second layer spaced apart from the first layer and the forming a plurality of vias that connect respective parallel conductive traces from the first and second layers to form a multilayer inductor comprises forming a plurality of sets of a first set of parallel conductive traces on the first layer, forming a plurality of sets of a second set of parallel conductive traces on the second layer spaced apart from the first layer and forming a plurality of sets of the plurality of vias that connect respective parallel conductive traces from the first and second layers to form a plurality of multilayer inductors.

18. The method of claim 17 , wherein the forming a first conductive plate on a third layer, the forming a second conductive plate on a fourth layer being spaced apart from third layer to form a multilayer capacitor and the forming a coupling via that connects the multilayer inductor to the multilayer capacitor comprises forming a plurality of sets of a first conductive plate on a third layer comprises forming a plurality of sets of a second conductive plate on a fourth layer being spaced apart from third layer to form a plurality of multilayer capacitors and forming a plurality of sets of a coupling via that connects the multilayer inductors to the multilayer capacitors.

19. The method of claim 18 , wherein the plurality of multilayer inductors and plurality of multilayer capacitors are arranged as a plurality of inductor-capacitor circuits interconnected with one another to form a multipole filter.

20. The method of claim 19 , further comprising coupling a plurality of tuning capacitors on opposing ends of each of the plurality of multilayer inductors and forming a plurality of sets of a plurality of space apart parallel vias arranged to form faraday cages to surround and isolate each of the multilayer inductor and associated tuning capacitors.