Systems, devices, and methods for interconnected processor topology
View Patent ↗An analog processor, for example a quantum processor may include a plurality of elongated qubits that are disposed with respect to one another such that each qubit may selectively be directly coupled to each of the other qubits via a single coupling device. Such may provide a fully interconnected topology.
1. An analog processor system comprising:
a plurality of quantum devices forming a fully interconnected topology of at least 5 quantum devices; and
a plurality of controllable coupling devices wherein there exists a controllable coupling device between each pair of quantum devices in the plurality of quantum devices.
2. The analog processor system of claim 1 wherein each quantum device in the plurality of quantum devices is a loop of superconducting material, wherein the loop of superconducting material is interrupted by one or more Josephson junctions.
3. The analog processor system of claim 1 wherein each quantum device in the plurality of quantum devices has a first basis state and a second basis state.
4. The analog processor system of claim 1 wherein each quantum device in the plurality of quantum devices is a plurality of serially ferromagnetically coupled loops of superconducting material wherein each loop is interrupted by one or more Josephson junctions.
5. The analog processor system of claim 4 wherein each pair of ferromagnetically coupled loops of superconducting material in the plurality of serially ferromagnetically coupled loops of superconducting material are ferromagnetically coupled by means of an intra-quantum device coupling device.
6. The analog processor system of claim 5 where the intra-quantum device coupling device transmits flux produced by a first loop of superconducting material in the pair of ferromagnetically coupled loops of superconducting material to a second loop of superconducting material in the pair of ferromagnetically coupled loops of superconducting material.
7. The analog processor system of claim 5 wherein the intra-quantum device coupling device is a loop of superconducting material, wherein the loop of superconducting material is interrupted by at least one Josephson junction.
8. The analog processor system of claim 5 wherein the intra-quantum device coupling device ensures the first loop of superconducting material and the second loop of superconducting material coexist within one of the group of a first basis state and a second basis state.
9. The analog processor system of claim 1 wherein the interconnected topology is capable of embedding a K n source graph, wherein there exists an edge between each node in the K n source graph and wherein n is a number of quantum devices comprising the plurality of quantum devices.
10. The analog processor system of claim 9 wherein the edge between a first node and a second node of the K n source graph is represented by a first controllable coupling device between a first quantum device and a second quantum device.
11. The analog processor system of claim 9 wherein the edge between a first node and a second node is labeled.
12. The analog processor system of claim 9 wherein the edge between a third node and a fourth node is an empty edge.
13. The analog processor system of claim 1 wherein each controllable coupling device is capable of producing an anti-ferromagnetic coupling state between a pair of quantum devices or a zero coupling state between a pair of quantum devices.
14. The analog processor system of claim 1 , further comprising:
a memory that stores information regarding at least one of: a coupling state corresponding to at least one of the controllable coupling devices or an initial basis state corresponding to at least one of the quantum devices.
15. The analog processor system of claim 14 wherein there is at least one communication path connecting the memory with an external system.
16. The analog processor system of claim 15 wherein the external system stores information regarding at least one of: a coupling state corresponding to at least one of the controllable coupling devices or an initial basis state corresponding to at least one of the quantum devices.
17. The analog processor system of claim 14 wherein at least a portion of the memory is superconducting.
18. The analog processor system of claim 14 wherein the initial basis state corresponds to at least a part of a known initial Hamiltonian wherein the known initial Hamiltonian is a mathematical description of a problem to be solved by the analog processor.
19. The analog processor system of claim 1 wherein each quantum device in the plurality of quantum devices is selected from the group consisting of superconducting flux qubits, superconducting charge qubits, superconducting phase qubits and superconducting hybrid qubits.
20. An analog processor system, comprising:
a plurality of qubit devices; and
a plurality of coupling devices, where at least one of the qubit devices is selectively directly coupleable to each of at least nine of the other qubit devices by respective single ones of the coupling devices.
21. The analog processor system of claim 20 wherein each of the qubit devices comprises a first elongated loop of superconducting material interrupted by at least one Josephson junction.
22. The analog processor system of claim 21 wherein each of the qubit devices further comprises a second elongated loop of superconducting material interrupted by at least one Josephson junction, and wherein each first elongated loop is ferromagnetically coupled to the second elongated loop by means of a coupling loop of superconducting material interrupted by at least one Josephson junction.
23. The analog processor system of claim 21 wherein each of the qubit devices further comprises a sequence of elongated loops of superconducting material, and wherein each first elongated loop is ferromagnetically coupled to the sequence of elongated loops by means of a coupling loop of superconducting material interrupted by at least one Josephson junction.
24. The analog processor system of claim 23 wherein each loop in the sequence of elongated loops is interrupted by at least on Josephson junction.
25. The analog processor system of claim 23 wherein at least one of the elongated loops in the sequence of elongated loops is directly ferromagnetically coupled to a preceding one of the elongated loops in the sequence of elongated loops and is directly ferromagnetically coupled to a following one of the elongated loops in the sequence of elongated loops.
26. The analog processor system of claim 20 wherein each qubit device exists in either a first basis state or a second basis state.
27. The analog processor system of claim 20 , further comprising:
a memory that stores information regarding at least one of: a coupling state corresponding to at least one of the coupling devices or an initial basis state corresponding to at least one of the qubit devices.
28. The analog processor system of claim 27 wherein there is at least one communication path connecting the memory with an external system.
29. The analog processor system of claim 28 wherein the external system stores information regarding at least one of: a coupling state corresponding to at least one of the controllable coupling devices or an initial basis state corresponding to at least one of the quantum devices.
30. The analog processor system of claim 27 wherein at least a portion of the memory administration system is superconducting.
31. The analog processor system of claim 27 wherein the initial basis state corresponds to at least a part of a known initial Hamiltonian wherein the known initial Hamiltonian is a mathematical description of a problem to be solved by the analog processor.
32. The analog processor system of claim 20 wherein each qubit device in the plurality of quantum devices is selected from the group consisting of superconducting flux qubits, superconducting charge qubits, superconducting phase qubits and superconducting hybrid qubits.
33. An analog processor, comprising:
a plurality of qubit devices, each of the qubit devices having an elongated loop of superconducting material interrupted by at least one Josephson junction; and
a plurality of coupling devices, each of the coupling devices operable to selectively couple a respective pair of the qubit devices, where at least one of the qubit devices is selectively directly coupleable to each of at least five nearest neighbor qubit devices as measured in a two dimensional plan view of the qubit devices by a respective single one of the coupling devices.
34. An analog processor, comprising:
a plurality of qubit devices, each of the qubit devices having an elongated loop of superconducting material interrupted by at least one Josephson junction; and
a plurality of coupling devices, each of the coupling devices operable to selectively couple a respective pair of the qubit devices, where at least one of the qubit devices is selectively directly coupleable to each of at least three nearest neighbor qubit devices as measured in a two dimensional plan view of the qubit devices by a respective single one of the coupling devices where each of the respective single one of the coupling devices extend parallel to one another in the two dimensional plan view.