Auto-detecting CMOS input circuit for single-voltage-supply CMOS
View Patent ↗An auto-detecting input circuit is operative to sustain relatively high voltages applied to an input pad and generate corresponding signal levels at a native supply voltage range. The input circuit includes floating wells, corresponding bias selectors, and input biasing transistors to ensure that no gate oxide exposed to external voltages sustains a voltage greater than a predefined value. Bias selectors select an available highest voltage to reverse bias corresponding floating wells and ensure transistors are not electrically overstressed. As input-related terminals experience switching related voltages, the bias selectors select alternate terminals to continue selection of the highest voltage available and provide correct reverse biasing conditions. A resistor and clamp generate translated output voltage levels limited to the native supply voltage range. A latch is triggered by a first input signal excursion above the native supply voltage. The latch output enables pull-down transistors to provide a correct low-level output signal.
1. An auto-detecting input circuit disposed between a supply-voltage terminal and a ground terminal, the auto-detecting input circuit comprising:
a clamp coupled to the supply-voltage terminal and an output pad and configured to electrically couple the output pad to the supply-voltage terminal;
a detector coupled to an input pad and configured to produce a detection signal;
a voltage-divider coupled between the input pad and the output pad and configured to translate input voltage levels to output voltage levels; and
a latch coupled to the voltage-divider and configured to retain a trigger signal;
wherein the detector comprises:
a first transistor with a source terminal coupled to the input pad, a gate terminal coupled to a drain terminal of the first transistor, and a bulk terminal coupled to a floating well; and
a second transistor with a source terminal coupled to the drain terminal of the first transistor, a gate terminal coupled to both an intermediate terminal and a drain terminal of the second transistor, and a bulk terminal coupled to the floating well.
2. The auto-detecting input circuit of claim 1 , wherein the detector comprises a bias selector coupled to the input pad, an intermediate terminal, and a well-bias terminal, the bias selector is configured to select a greatest magnitude voltage level present on either the input pad or the intermediate terminal and provide the selected voltage level to the well-bias terminal.
3. The auto-detecting input circuit of claim 1 , wherein the voltage-divider comprises:
a resistor with a first current carrying node coupled to the input pad, a second current carrying node coupled to the output pad, and a third terminal coupled to the ground terminal;
a first transistor with a source terminal coupled to the output pad, a gate terminal coupled to an output terminal of the latch, a drain terminal coupled to the ground terminal, and a bulk terminal coupled to the supply-voltage terminal; and
a second transistor with a source terminal and a bulk terminal coupled to the ground terminal, a gate terminal coupled to an output terminal of the latch, and a drain terminal coupled to the output pad;
wherein the voltage-divider is configured to be activated by the trigger signal.
4. The auto-detecting input circuit of claim 1 , wherein the clamp circuit comprises:
a first transistor with a source terminal and a bulk terminal coupled to the supply-voltage terminal and a gate terminal coupled to a drain terminal of the first transistor;
a second transistor with a drain terminal coupled to the drain terminal of the first transistor, a gate terminal coupled to the output pad, and a source terminal and a bulk terminal coupled to the ground terminal; and
a third transistor with a first current carrying terminal coupled to the ground terminal, a gate terminal coupled to the drain terminal of the first transistor, a second current carrying terminal coupled to the output pad, and a bulk terminal coupled to the supply-voltage terminal;
wherein the clamp circuit is configured to be activated by an elevated high-logic level on the output pad and to clamp the output pad to an off-set voltage level.
5. The auto-detecting input circuit of claim 1 , further comprising a trigger circuit, the trigger circuit comprising:
a first transistor with a source terminal coupled to an intermediate terminal, a gate terminal coupled to the supply-voltage terminal, a bulk terminal coupled to a floating well;
a second transistor with a drain terminal coupled to the drain terminal of the first transistor, a gate terminal coupled to the supply-voltage terminal, a source terminal coupled to a trigger output terminal, and a bulk terminal coupled to the ground terminal; and
a capacitor coupled to the trigger output terminal, and a ground terminal;
wherein the trigger circuit is configured to generate the trigger signal corresponding to the detection signal.
6. The auto-detecting input circuit of claim 1 , further comprising a trigger circuit, the trigger circuit comprising a bias selector, the bias selector comprising:
a first transistor with a first current carrying terminal coupled to an intermediate terminal, a gate terminal coupled to the supply-voltage terminal, a second current carrying terminal coupled to a floating well, and a body terminal coupled to the floating well; and
a second transistor with a first current carrying terminal coupled to the floating well, a gate terminal coupled to the intermediate terminal, a second current carrying terminal coupled to the supply-voltage terminal, and a body terminal coupled to the floating well.
7. The auto-detecting input circuit of claim 1 , further comprising a trigger circuit, the trigger circuit comprising a bias selector coupled to the supply-voltage terminal, an intermediate terminal, and a floating well, the bias selector configured to select a greatest magnitude voltage level present on either the supply-voltage terminal or the intermediate terminal and provide the selected voltage level to the floating well.
8. The auto-detecting input circuit of claim 1 , wherein the latch comprises:
a first inverter with an input terminal coupled to the detector, a first power terminal coupled to the supply-voltage terminal, a second power terminal coupled to the ground terminal, and an output terminal; and
a second inverter with an input terminal coupled to the output terminal of the first inverter, a first power terminal coupled to the supply-voltage terminal, a second power terminal coupled to the ground terminal, and an output terminal coupled to the input terminal of the first inverter;
wherein the first inverter and the second inverter are cross-coupled and configured to be a latch loop.
9. The auto-detecting input circuit of claim 1 , further comprising a transistor with a source terminal coupled to an intermediate terminal, a gate terminal and a drain terminal coupled to the supply-voltage terminal, and a bulk terminal coupled to a floating well, the transistor configured to generate a bias level on the intermediate terminal when an elevated input voltage is received on the input pad.
10. An auto-detecting input circuit disposed between a supply-voltage terminal and a ground terminal, the auto-detecting input circuit comprising:
a clamp coupled to the supply-voltage terminal and an output pad and configured to electrically couple the output pad to the supply-voltage terminal;
a detector coupled to an input pad and configured to produce a detection signal;
a voltage-divider coupled between the input pad and the output pad and configured to translate input voltage levels to output voltage levels; and
a latch coupled to the voltage-divider and configured to retain a trigger signal;
wherein the detector comprises a bias selector, the bias selector comprising:
a first transistor with a first current carrying terminal coupled to the input pad, a gate terminal coupled to an intermediate terminal, a second current carrying terminal coupled to a floating well, and a body terminal coupled to the floating well; and
a second transistor with a first current carrying terminal coupled to the floating well, a gate terminal coupled to the input pad, a second current carrying terminal coupled to the intermediate terminal, and a body terminal coupled to the floating well.