Method of manufacturing a thin-film transistor substrate

1. A method of manufacturing a thin-film transistor (TFT) substrate, comprising:

sequentially forming a gate insulation layer, a semiconductor layer, an ohmic contact layer, and a data metal layer on a substrate having a gate wire formed thereon;

forming a photoresist pattern in a source electrode area and a drain electrode area, the photoresist pattern including a binder having a degree of dispersion of about 1.5 to about 2;

etching the data metal layer using the photoresist pattern as a first etch-stop layer to form a data wire including a source electrode and a drain electrode;

reflowing the photoresist pattern to cover a channel region between the source electrode and the drain electrode;

etching the ohmic contact layer and the semiconductor layer using the reflowed photoresist pattern as a second etch-stop layer to form an active pattern including an ohmic contact pattern and a semiconductor pattern;

etching-back the reflowed photoresist pattern to expose a portion of the ohmic contact pattern in the channel region; and

etching the ohmic contact pattern using the etched-back photoresist pattern as a third etch-stop layer, completing the TFT having a channel.

2. The method of claim 1 , wherein the photoresist pattern comprises a novolak resin or an acrylic resin.

3. The method of claim 2 , wherein the photoresist pattern is reflowed at a temperature range of about 150° C. to about 160° C.

4. The method of claim 2 , wherein the photoresist pattern is reflowed at a temperature range of about 150° C. to about 160° C.

5. The method of claim 1 , wherein the photoresist pattern is reflowed at a temperature range of about 150° C. to about 160° C.

6. The method of claim 1 , wherein the photoresist pattern is reflowed at a temperature range of about 150° C. to about 160° C.

7. The method of claim 1 , further comprising:

stripping the etched-back photoresist pattern;

forming an overcoat layer on the substrate having the data wire formed thereon; and

forming a pixel electrode electrically connected to the drain electrode on the overcoat layer.

8. The method of claim 7 , further comprising:

forming an organic layer on the overcoat layer.

9. The method of claim 7 , further comprising:

forming a storage capacitor.

10. The method of claim 9 , wherein forming the storage capacitor comprises:

forming a lower storage electrode, which is spaced apart from the gate wire, from a same layer as the gate wire; and

forming an upper storage electrode, which overlaps with the lower storage electrode, from a same layer as the data wire.

11. The method of claim 9 , wherein forming the storage capacitor comprises forming a lower storage electrode, which is spaced apart from the gate wire, from a same layer as the gate wire, and

wherein the pixel electrode overlaps with the lower storage electrode to form an upper storage electrode of a TFT.

12. A method of manufacturing a TFT substrate, comprising:

sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on a substrate having a gate wire and a gate metal pad formed thereon;

forming a contact hole passing through the gate insulation layer, the semiconductor layer and the ohmic contact layer to expose the gate metal pad;

forming a data metal layer on the substrate having the contact hole;

forming a photoresist pattern in a source electrode region, a drain electrode region and a pad region, the photoresist pattern including a binder having a degree of dispersion of about 1.5 to about 2;

etching the data metal layer using the photoresist pattern as a first etch-stop layer to form a data wire including a source electrode and the drain electrode and a data metal pad directly connected to the gate metal pad;

reflowing the photoresist pattern to cover a channel region between the source electrode and the drain electrode;

etching the ohmic contact layer and the semiconductor layer using the reflowed photoresist pattern as a second etch-stop layer to form an active pattern including ah ohmic contact pattern and a semiconductor pattern;

etching-back the reflowed photoresist pattern to expose a portion of the ohmic contact pattern in the channel region; and

etching the ohmic contact pattern using the etched-back photoresist pattern as a third etch-stop layer, completing the TFT having a channel.

13. The method of claim 12 , wherein the photoresist pattern comprises a novolak resin or an acrylic resin.

14. The method of claim 13 , wherein reflowing the photoresist pattern is performed at a temperature range of about 150° C. to about 160° C.

15. The method of claim 13 , wherein the photoresist pattern is reflowed at a temperature range of about 150° C. to about 160° C.

16. The method of claim 12 , wherein the photoresist pattern is reflowed at a temperature range of about 150° C. to about 160° C.

17. The method of claim 12 , wherein the photoresist pattern is reflowed at a temperature range of about 150° C. to about 160° C.

18. The method of claim 12 , further comprising:

stripping the etched-back photoresist pattern;

forming an overcoat layer on the substrate having the data wire formed thereon; and

forming a pixel electrode electrically connected to the drain electrode and a pad electrode connected to the data metal pad on the overcoat layer.

19. The method of claim 18 , further comprising:

forming an organic layer on the overcoat layer.

20. The method of claim 18 , further comprising forming a storage capacitor by:

forming a lower storage electrode, which is spaced apart from the gate wire, from a same layer as the gate wire; and

forming an upper storage electrode, which overlaps with the lower storage electrode, from a same layer as the data wire.

21. The method of claim 18 , further comprising forming a lower storage electrode, which is spaced apart from the gate wire, from a same layer as the gate wire to form a storage capacitor, and

wherein the pixel electrode overlaps with the lower storage electrode to form an upper storage electrode.

22. A method of manufacturing a thin-film transistor (TFT) substrate, comprising:

sequentially forming a gate insulation layer, a semiconductor layer, an ohmic contact layer, and a data metal layer on a substrate having a gate wire formed thereon;

forming a photoresist pattern in a source electrode area and a drain electrode area the photoresist pattern including a binder having a degree of dispersion of about 1.5 to about 2;

etching the data metal layer using the photoresist pattern as a first etch-stop layer to form a data wire including a source electrode and a drain electrode;

reflowing the photoresist pattern to cover a channel region between the source electrode and the drain electrode;

etching the ohmic contact layer and the semiconductor layer using the reflowed photoresist pattern as a second etch-stop layer to form an active pattern including an ohmic contact pattern and a semiconductor pattern;

etching-back the reflowed photoresist pattern to expose a portion of the ohmic contact pattern in the channel region;

stripping the etched-back photoresist pattern;

forming an overcoat layer on the substrate having the data wire formed thereon; and

forming a pixel electrode electrically connected to the drain electrode and a pad electrode connected to the data metal pad on the overcoat layer.