IP Library Granted Patent US 7,738,119
Granted Patent B2
US 7,738,119 · App. 12/015,849 · Granted Jun 15, 2010

Optical inspection system for a wafer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,738,119
App. No.
12/015,849
Granted
Jun 15, 2010
Kind
B2
Abstract

Provided is an optical inspection system for a semiconductor wafer, by which a threshold value optimal for inspection can be determined and optical inspection of each chip can be performed based on the threshold value, by obtaining in advance a table indicating a relation between a film thickness of a thin film in specific positions in the wafer and a gradation value for each sample area in the chip, measuring the film thickness of the thin film in the specific positions of the wafer to be inspected before inspecting the chip, and comparing the measured film thickness with the gradation value in the table.

Claims (11)

1. An optical inspection method for checking acceptability of circuits formed on the semiconductor wafer, comprising:

measuring thicknesses of a film disposed on the semiconductor wafer at a plurality of locations on the semiconductor wafer;

measuring levels of gradation at the plurality of locations on the semiconductor wafer;

calculating a sensitivity curve representative of a relation between the measured levels of gradation and the measured thicknesses;

determining acceptable ranges of gradation at one or more points in a representative circuit, from the sensitivity curve read at film thicknesses measured at the one or more points, wherein at least one representative circuit is selected from each of one or more areas defined over the semiconductor wafer; and

determining whether levels of gradation measured in a respective circuit in each area fall within the acceptable ranges of gradation determined from the at least one representative circuit located in the corresponding area in order to determine the acceptability of the respective circuit.

2. The method according to claim 1 , wherein the film is a silicon oxide film formed on a silicon substrate.

3. The method according to claim 1 , wherein the film is a silicon nitride film formed on a silicon substrate or a silicon oxide film.

4. The method according to claim 1 , wherein the film is a polycrystalline silicon film formed on a silicon oxide film.

5. The method according to claim 1 , wherein measuring thicknesses of a film uses an ellipsometer.

6. The method according to claim 1 , wherein measuring thicknesses of a film is performed at a time of wafer alignment.

Assignments (3)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →