Granted Patent B2

US 8,055,982 · App. 12/016,577 · Granted Nov 8, 2011

Abstract

Claims (48)

1. A method comprising:

receiving payload data from a data source at error correction code (ECC) logic, the ECC logic adapted to process a block of data of a particular size via a plurality of stages;

initializing the ECC logic to a selected stage of the plurality of stages, the selected stage including an initial value and an initial number of cycles related to a number of symbols of padding data corresponding to a difference in size between the payload data and the block of data, the selected stage related to a state of the ECC logic as if the number of symbols of padding data had already been processed by the ECC logic; and

processing the payload data via the ECC logic beginning with the selected stage of the plurality of stages to produce parity data related to the payload data.

2. The method of claim 1 , wherein the ECC logic comprises a state machine that is initialized based on the initial value and the initial number of cycles.

3. The method of claim 1 , further comprising:

receiving parity data from the data source; and

comparing the parity data from the data source to the parity data produced by the ECC logic to perform error checking of the payload data.

4. The method of claim 3 , further comprising detecting an error in the payload data and correcting the error using the received parity data.

5. The method of claim 1 , wherein the ECC logic uses Reed-Solomon error correction codes.

6. The method of claim 1 , further comprising retrieving the initial value and the initial number of cycles from a read only memory.

7. The method of claim 1 , further comprising storing the initial value and the initial number of cycles in a memory by hard coding the initial value and the initial number of cycles into the error correction code (ECC) engine.

8. The method of claim 1 , wherein the data source comprises a flash memory.

9. The method of claim 1 , wherein the data source comprises a non-volatile memory.

10. The method of claim 1 , wherein the data source comprises a communications channel.

11. The method of claim 1 , wherein initializing the ECC logic comprises retrieving the selected stage from an initialization register.

12. An error correction code (ECC) engine comprising:

a memory to store a value and a number of cycles related to an intermediate stage; and

error correction code (ECC) logic to process a data block via a plurality of stages including an initial stage and the intermediate stage, the ECC logic to receive payload data from a data source, the ECC logic to read the value and the number of cycles from the memory, the ECC logic to process the payload data starting from the intermediate stage;

wherein the payload data is smaller than the data block by a number of symbols; and

wherein the value and the number of cycles relate to a number of cycles of the ECC logic to process the number of symbols.

13. The system of claim 12 , wherein the data source comprises a non-volatile memory.

14. The system of claim 12 , wherein the memory comprises an initialization register.

15. The system of claim 12 , wherein the intermediate stage is hard coded into the memory.

16. The system of claim 12 , wherein the ECC logic includes logic to generate new parity data from the payload data and to compare the new parity data to the parity data from the data source.

17. A method comprising:

receiving payload data and associated parity data from a data source, wherein the payload data has a size that is smaller than a desired size of a data block;

initializing error correction code (ECC) logic to an intermediate state value and an intermediate number of cycles related to a difference between a size of the payload data and the desired size of the data block;

processing the payload data using the ECC logic to produce processed parity data; and

comparing the processed parity data to the associated parity data.

18. The method of claim 17 , further comprising:

determining the intermediate state value and the intermediate number of cycles of the ECC logic during a design process, the intermediate state value and the intermediate number of cycles relating to a state of the ECC logic after processing padding data, the padding data corresponding to a number of symbols related to a difference between a size of the payload data and the desired size of the data block; and

storing the intermediate state value and the intermediate number of cycles in a memory.

19. The method of claim 18 , wherein initializing the ECC logic comprises:

retrieving the intermediate state value and the intermediate number of cycles from the memory; and

initializing a state machine of the ECC logic to the intermediate state based on the initial state value and the initial number of cycles.

20. A processor readable storage medium embodying processor readable instructions, that when executed by the processor, cause the processor to perform error detection and correction on payload data using associated parity data, the processor readable instructions comprising:

instructions to initialize error correction code (ECC) logic to an intermediate value and an intermediate number of cycles in response to receiving payload data from a data source, wherein the ECC logic processes a data block of a desired size using a plurality of stages; and

instructions to calculate parity data for the payload data using the ECC logic;

wherein the intermediate value and the intermediate number of cycles relate to a state of the ECC logic after processing a number of symbols of padding data related to a difference between the desired size of the data block and a size of the payload data.

21. The processor readable medium of claim 20 , wherein the processor readable instructions further comprise instructions to detect and to correct errors in the payload data using the parity data.

22. The processor readable medium of claim 20 , wherein the data source comprises a non-volatile memory.

23. The processor readable medium of claim 20 , wherein the data source comprises a random access memory (RAM).

24. A method comprising:

receiving payload data at error correct code (ECC) logic adapted to process a data block of a particular number of symbols;

determining a difference between a number of symbols of the payload data and the particular number of symbols of the data block;

selecting an intermediate stage from a plurality of stages, where each stage of the plurality of stages corresponds to a value and a number of cycles of the ECC logic after processing a number of symbols of padding data corresponding to the difference; and

processing the payload data using the ECC logic initialized to the selected intermediate stage.

Assignments (26)