Sense amplifier for non-volatile memories

1. A sense amplifier for reading a memory cell, the sense amplifier comprising:

a read node linked to the memory cell;

an active stage connected to the read node and comprising means for supplying a read current on the read node using a MOS transistor having a threshold voltage;

a data output linked to a node of the active stage where a voltage appears which is representative of a state of conductivity of the memory cell; and

means for maintaining a voltage (Vs) on the read node at a lower value than the threshold voltage, having:

a first transistor and a second transistor arranged in series in the active stage, the second transistor being linked to the read node; and

means for applying, to gate terminals of the first and second transistors, respective gate voltages having a controlled potential difference relative to each other.

2. A sense amplifier according to claim 1 , comprising a control stage biased by a bias current, the control stage including an impedance having a bias current flowing therethrough that determines the potential difference between the gate voltages applied to the first and second transistors.

3. A sense amplifier according to claim 2 , comprising means for generating the bias current flowing through the impedance independently from a current flowing through the active stage.

4. A sense amplifier according to claim 3 , wherein the means for generating the bias current flowing through the impedance comprise a resistor through which the bias current is generated, the voltage Vs on the read node complying with the following relationship:

Vs=Vtn (1 −R 1 /R 11)

where Vtn is the threshold voltage, R 1 is an impedance value of the impedance and R 11 is a resistance value of the resistor.

5. A sense amplifier according to claim 2 , comprising means for limiting a voltage drop in the impedance during a phase of precharging the read node.

6. A sense amplifier according to claim 5 , wherein the means for limiting the voltage drop in the impedance comprise a transistor mounted in parallel with the impedance, controlled by the voltage on the read node.

7. A sense amplifier according to claim 2 , wherein the impedance comprises an element of the group comprising a resistor and a transistor.

8. A sense amplifier according to claim 2 , comprising means for discharging a connection node between the first and the second transistors, and thus avoiding a blocking situation.

9. A sense amplifier according to claim 8 , wherein the means for discharging the connection node between the first and the second transistors comprise a transistor connected between the connection node and ground.

10. A sense amplifier according to claim 8 , comprising means for attenuating oscillations appearing in the connection node.

11. A sense amplifier according to claim 10 wherein said means for attenuating oscillations comprise a capacitor connected to said connection node.

12. A sense amplifier according to claim 2 , wherein the active stage comprises:

a first current generator coupled to the read node through said first and second transistors; and

the control stage comprises a second current generator supplying the bias current flowing through the impedance.

13. A sense amplifier according to claim 1 , comprising means for activating the sense amplifier before a phase for precharging the read node.

14. A sense amplifier according to claim 13 , wherein the means for activating the sense amplifier before the phase of precharging the read node comprise means for disconnecting the sense amplifier from the read node during the activation of the sense amplifier.

15. A non-volatile memory, comprising:

a memory cell; and

a sense amplifier for reading the memory cell, wherein the sense amplifier comprises:

a read node linked to the memory cell;

an active stage connected to the read node and comprising means for supplying a read current on the read node using a MOS transistor having a threshold voltage;

a data output linked to a node of the active stage where a voltage appears which is representative of a state of conductivity of the memory cell; and

means for maintaining a voltage (Vs) on the read node at a lower value than the threshold voltage, having:

a first transistor and a second transistor arranged in series in the active stage, the second transistor being linked to the read node; and

means for applying, to gate terminals of said first and second transistors, respective gate voltages having a controlled potential difference relative to each other.

16. A non-volatile memory according to claim 15 , wherein the sense amplifier comprises a control stage biased by a bias current, the control stage including an impedance having a bias current flowing through that determines the potential difference between the gate voltages applied to the first and second transistors.

17. A non-volatile memory according to according to claim 16 , wherein the sense amplifier comprises means for generating the bias current flowing through the impedance independently from a current flowing through the active stage.

18. A non-volatile memory according to claim 17 , wherein the means for generating the bias current flowing through the impedance comprise a resistor through which the bias current is generated, the voltage Vs on the read node complying with the following relationship:

Vs=Vtn (1 −R 1 /R 11)

where Vtn is the threshold voltage, R 1 is an impedance value of the impedance and R 11 is a resistance value of the resistor.

19. A sense amplifier comprising:

a read node able to be coupled to a memory cell;

an active stage coupled to said read node;

a MOS selection transistor coupled to said read node and having a threshold voltage; and

an active circuit structured to maintain a voltage on the read node lower than said threshold voltage, the active circuit including:

two transistors in series with each other and coupled to the read node; and

a control circuit structured to maintain a potential difference between the gates of said two transistors.

20. A sense amplifier according to claim 19 , comprising a control stage biased by a bias current, the control stage including an impedance having a bias current flowing through that determines a potential difference between the gate voltages applied to the first and second transistors.

21. A method of reading a memory cell comprising:

selecting the memory cell;

connecting the memory cell to a read node of a sense amplifier;

supplying a read current on the read node using a MOS transistor of the sense amplifier, the MOS transistor having a threshold voltage; and

maintaining a read voltage on the read node at a value lower than the threshold voltage, wherein maintaining the read voltage of the read node at a lower value than the threshold voltage comprises:

arranging a first transistor and a second transistor in series in the sense amplifier, the second transistor being linked to the read node; and

applying, to gate terminals of the first and second transistors, respective gate voltages having a controlled potential difference relative to each other.

22. A method according to claim 21 comprising:

biasing a control stage of the sense amplifier by a bias current; and

determining a potential difference between gate voltages of the first and second transistors and using an impedance through which the bias current flows.

23. A method according to claim 22 comprising generating the bias current flowing through the impedance independently from a current flowing through the active stage of the sense amplifier.

24. A method according to claim 23 wherein the bias current flowing through the impedance is generated through a resistor, the voltage Vs on the read node complying with the following relationship:

Vs=Vtn (1−1 R 1 /R 11)

where Vtn is the threshold voltage, R 1 is an impedance value of the impedance and R 11 is a resistance value of the resistor.