Using address and non-address information for improved index generation for cache memories
View Patent ↗Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
1. A method for generating an index for a cache memory, comprising:
receiving a request to access a cache memory, wherein the request includes address information;
obtaining non-address information associated with the request, wherein obtaining the non-address information comprises at least one of:
obtaining information from an instruction that caused the request, or
obtaining a parameter from at least one component in a computer system in which the cache memory is located;
generating the index using the address information and the non-address information;
upon detecting a first switching condition while generating indices using address information and non-address information, switching from generating indices using address information and non-address information to generating indices using only address information;
upon detecting a second switching condition while generating indices using only address information, switching from generating indices using address information and non-address information to generating indices using only address information; and
using the index to access the cache memory.
2. The method of claim 1 , wherein receiving the request involves receiving one of a request for: a data-cache access; an instruction-cache access; a TLB write; a TLB lookup; or a way prediction.
3. The method of claim 1 , wherein the information from the instruction that caused the request comprises at least one of:
an instruction type or opcode;
a destination register address;
a source register address;
an immediate value; or
control information.
4. The method of claim 1 , wherein the parameter from the at least one component in the computer system comprises at least one of:
a parameter from a processor, a cache, or another component in the computer system; or
a derived parameter computed from one or more parameters from at least one of the processor, the cache, or another component in the computer system.
5. The method of claim 1 , wherein generating the index involves prepending, appending, interleaving, or combining some or all of the address information to some or all of the non-address information.
6. The method of claim 1 , wherein generating the index involves logically combining some or all of the address information with some or all of the non-address information.
7. The method of claim 6 , wherein logically combining the address information with the non-address information involves computing a bitwise XOR of some or all of the address information with some or all of the non-address information.
8. The method of claim 1 , wherein generating the index involves computing the index using a function, wherein the inputs to the function include some or all of the address information and some or all of the non-address information.
9. An apparatus for generating an index for a cache memory, comprising:
a receiving mechanism configured to receive a request to access a cache memory, wherein the request includes address information;
an obtaining mechanism configured to obtain non-address information associated with the request, wherein obtaining the non-address information comprises at least one of:
obtaining information from an instruction that caused the request, or
obtaining a parameter from at least one component in a computer system in which the cache memory is located;
a generation mechanism configured to generate the index using the address information and the non-address information; and
an accessing mechanism configured to use the index to access the cache memory,
wherein, upon detecting a first switching condition while generating indices using address information and non-address information, the generation mechanism is configured to switch from generating indices using address information and non-address information to generating indices using only address information; and
wherein, upon detecting a second switching condition while generating indices using only address information, the generation mechanism is configured to switch from generating indices using address information and non-address information to generating indices using only address information.
10. The apparatus of claim 9 , wherein the receiving mechanism is configured to receive one of a request for: a data-cache access; an instruction-cache access; a TLB write; a TLB lookup; or a way prediction.
11. The apparatus of claim 9 , wherein the information from the instruction that caused the request comprises at least one of:
an instruction type or opcode;
a destination register address;
a source register address;
an immediate value; or
control information.
12. The apparatus of claim 9 , wherein the parameter from the at least one component in the computer system comprises at least one of:
a parameter from a processor, a cache, or another component in the computer system; or
a derived parameter computed from one or more parameters from at least one of the processor, the cache, or another component in the computer system.
13. The apparatus of claim 9 , wherein when generating the index, the generation mechanism is configured to prepend, append, interleave, or combine some or all of the address information to some or all of the non-address information.
14. The apparatus of claim 9 , wherein when generating the index, the generation mechanism is configured to logically combine some or all of the address information with some or all of the non-address information.
15. The apparatus of claim 14 , wherein when logically combining the address information with the non-address information, the generation mechanism is configured to compute a bitwise XOR of some or all of the address information with some or all of the non-address information.
16. The apparatus of claim 9 , wherein when generating the index, the generation mechanism is configured to compute the index using a function, wherein the inputs to the function include some or all of the address information and some or all of the non-address information.
17. A computer system for generating an index for a cache memory, comprising:
a processor coupled to the cache memory, wherein the cache memory stores data for the processor;
a receiving mechanism configured to receive a request to access a cache memory, wherein the request includes address information;
an obtaining mechanism configured to obtain non-address information associated with the request, wherein obtaining the non-address information comprises at least one of:
obtaining information from an instruction that caused the request, or
obtaining a parameter from at least one component in a computer system in which the cache memory is located;
a generation mechanism configured to generate the index using the address information and the non-address information; and
an accessing mechanism configured to use the index to access the cache memory,
wherein, upon detecting a first switching condition while generating indices using address information and non-address information, the generation mechanism is configured to switch from generating indices using address information and non-address information to generating indices using only address information; and
wherein, upon detecting a second switching condition while generating indices using only address information, the generation mechanism is configured to switch from generating indices using address information and non-address information to generating indices using only address information.
18. The computer system of claim 17 , wherein the information from the instruction that caused the request comprises at least one of:
an instruction type or opcode;
a destination register address;
a source register address;
an immediate value; or
control information.
19. The computer system of claim 17 , wherein the parameter from the at least one component in the computer system comprises at least one of:
a parameter from a processor, a cache, or another component in the computer system; or
a derived parameter computed from one or more parameters from at least one of the processor, the cache, or another component in the computer system.
20. The computer system of claim 17 , wherein when generating the index, the generation mechanism is configured to prepend, append, interleave, or combine some or all of the address information to some or all of the non-address information.
21. The computer system of claim 17 , wherein when generating the index, the generation mechanism is configured to logically combine some or all of the address information with some or all of the non-address information.
22. The computer system of claim 17 , wherein when generating the index, the generation mechanism is configured to compute the index using a function, wherein the inputs to the function include some or all of the address information and some or all of the non-address information.