Thin film transistor array panel
View Patent ↗A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.
1. A thin film transistor array panel comprising:
a substrate;
a first gate line disposed on the substrate;
a second gate line disposed on the substrate and separated from the first gate line;
a data line intersecting the first and second gate lines;
a first thin film transistor connected to the first gate line and the data line;
a second thin film transistor connected to the first gate line and the data line;
a third thin film transistor connected to the second gate line and having a drain electrode; and
a pixel electrode including a first subpixel electrode and a second subpixel electrode,
wherein
the first subpixel electrode is connected to the first and third thin film transistor,
the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and
the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.
2. The thin film transistor array panel of claim 1 , wherein edges of the projection and edges of the drain electrode form two intersections.
3. The thin film transistor array panel of claim 1 , wherein edges of the projection and edges of the drain electrode form four intersections.
4. The thin film transistor array panel of claim 3 , wherein the projection further comprises a second pair of edge portions that meet a second edge of the drain electrode and are substantially parallel to each other, and a distance between the edge portions in the first pair along a first direction is substantially the same as a distance between the edge portions in the second pair along the first direction.
5. The thin film transistor array panel of claim 4 , wherein the first edge and the second edge of the drain electrode comprises a first pair of drain edge portions substantially parallel to each other and a second pair of drain edge portions substantially parallel to each other.
6. The thin film transistor array panel of claim 5 , wherein a distance between the edge portions in the first pair of drain edge portions along a second direction substantially perpendicular to the first direction is substantially the same as a distance between the edge portions in the second pair of drain edge portions along the second direction.
7. The thin film transistor array panel of claim 6 , wherein the edge portions and the drain edge portions are equal to or longer than twice an alignment error range.
8. The thin film transistor array panel of claim 6 , wherein the projection has a shape of a bar and passes through the drain electrode.
9. The thin film transistor array panel of claim 8 , wherein the projection has a uniform width.
10. The thin film transistor array panel of claim 9 , wherein the drain electrode has a uniform width.
11. The thin film transistor array panel of claim 6 , wherein the projection has a branch fully overlapping the drain electrode.
12. The thin film transistor array panel of claim 1 , further comprising a storage electrode overlapping the drain electrode.