Extension of accuracy of a flash ADC by 1-bit through interpolation of comparator outputs
View Patent ↗ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an interpolating comparator. The interpolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.
1. An analog-to-digital converter (ADC), comprising:
a comparator array, the array comprising a plurality of comparator blocks, each block comprising a primary comparator and an interpolating comparator, the interpolating comparator comparing opposite polarity voltage outputs of adjacent primary comparators of the plurality of blocks to generate a least significant bit; and
a binary converter, coupled to the array, that converts array output to binary code.
2. The ADC of claim 1 , wherein each primary comparator is associated with a different static reference voltage.
3. The ADC of claim 1 , wherein the binary converter converts array output to binary code via a decoder communicatively coupled to the comparator array and binary converter that first converts array output to a Gray code, and wherein the binary converter converts the Gray code to binary code.
4. The ADC of claim 1 , wherein each block further comprises a NOR gate communicatively coupled to the interpolating comparator.
5. The ADC of claim 4 , further comprising an OR gate communicatively coupled to the NOR gates of the array.
6. A method, comprising:
receiving an analog input signal;
comparing the signal to reference voltages using an array of primary comparators;
interpolating between reference voltages by comparing opposite polarity voltage outputs of adjacent primary comparators to generate a least significant bit; and
converting comparison results to a binary code.
7. The method of claim 6 , wherein the converting includes first converting the comparison results to a Gray code and subsequently converting the Gray code to binary code.
8. The method of claim 6 , wherein the using includes passing the interpolation results to a NOR gate.
9. The method of claim 8 , wherein the using further includes passing output of the NOR gate to an OR gate.
10. A system, comprising:
means for receiving an analog input signal;
an array of primary comparators for comparing the signal to reference voltages;
means for interpolating between reference voltages by comparing opposite polarity voltage outputs of adjacent primary comparators to generate a least significant bit; and
means for converting comparison results to a binary code.