Semiconductor integrated circuit device and data processor system
View Patent ↗To provide an input interface technique of display data which can contribute to improvement of reliability and high performance of a system in which a semiconductor integrated circuit device including a RAM and a display driver circuit is incorporated. A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
1. A semiconductor integrated circuit device comprising:
a first high-speed serial interface circuit which has one differential serial data channel;
a second high-speed serial interface circuit which has a plurality of differential serial data channels;
a control circuit which controls an internal operation in accordance with control information that is input to the first high-speed serial interface circuit from the outside;
a RAM to which data information that is input to the first high-speed serial interface circuit from the outside and data information that is input to the second high-speed serial interface circuit from the outside can be supplied; and
a display driver circuit which generates a display driving signal on the basis of the data information read from the RAM,
wherein whether the first high-speed serial interface circuit or the second high-speed serial interface circuit is used when receiving the data information to be supplied to the RAM is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the control circuit uses a first frame synchronization signal input from an external terminal in a RAM operation for the data information that is input to the first high-speed serial interface circuit, and uses a second frame synchronization signal reproduced by using strobe information in a RAM operation for the data information that is input to the second high-speed serial interface circuit, the strobe information being input from the second high-speed serial interface circuit.
3. The semiconductor integrated circuit device according to claim 2 ,
wherein the first high-speed serial interface circuit is a mobile digital data interface circuit which inputs the data information and the control information in synchronization with a differential strobe signal.
4. The semiconductor integrated circuit device according to claim 3 ,
wherein the second high-speed serial interface circuit is a mobile video interface circuit which inputs the data information and the strobe information in synchronization with a clock signal.
5. The semiconductor integrated circuit device according to claim 2 ,
wherein when supplying the data information input to the first high-speed serial interface circuit to the RAM, the control circuit starts reproducing of the second frame synchronization signal in response to a switching instruction by the control information, and starts writing of the data information input to the second high-speed serial interface circuit into the RAM in synchronization with the second frame synchronization signal after writing of the data information for one frame in synchronization with the first frame synchronization signal is completed.
6. The semiconductor integrated circuit device according to claim 5 ,
wherein when supplying the data information input to the second high-speed serial interface circuit to the RAM, the control circuit starts writing of the data information input to the first high-speed serial interface circuit into the RAM in synchronization with the first frame synchronization signal after writing of the data information for one frame in synchronization with the second frame synchronization signal is completed in response to a switching instruction by the control information.
7. A data processor system comprising:
a host processor;
an accelerator which is coupled to the host processor;
a display driving control device which is coupled to the host processor and the accelerator; and
a display device which is coupled to the display driving control device,
wherein the display driving control device including:
a first high-speed serial interface circuit which is coupled to the host processor and which has one differential serial data channel;
a second high-speed serial interface circuit which is coupled to the accelerator and which has a plurality of differential serial data channels;
a control circuit which controls an internal operation in accordance with control information that is input to the first high-speed serial interface circuit from the host processor;
a RAM to which data information that is input to the first high-speed serial interface circuit from the host processor and data information that is input to the second high-speed serial interface circuit from the accelerator can be supplied; and
a display driver circuit which generates a display driving signal on the basis of the data information read from the RAM to output to the display device,
wherein whether the first high-speed serial interface circuit or the second high-speed serial interface circuit is used when receiving the data information to be supplied to the RAM is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
8. The data processor system according to claim 7 ,
wherein the host processor is a baseband processor which is coupled to a high-frequency circuit, and the accelerator is a microcomputer which executes a command issued from the baseband processor.
9. The data processor system according to claim 8 mounted in a mobile communication terminal device.
10. The data processor system according to claim 7 ,
wherein the control circuit uses a first frame synchronization signal input from the host processor in a RAM operation for the data information that is input to the first high-speed serial interface circuit, and uses a second frame synchronization signal reproduced by using strobe information in a RAM operation for the data information that is input to the second high-speed serial interface circuit, the strobe information being input from the accelerator.
11. The data processor system according to claim 10 ,
wherein the first high-speed serial interface circuit is a mobile digital data interface circuit which inputs the data information and the control information in synchronization with a differential strobe signal.
12. The data processor system according to claim 11 ,
wherein the second high-speed serial interface circuit is a mobile video interface circuit which inputs the data information and the strobe information in synchronization with a clock signal.
13. The data processor system according to claim 7 ,
wherein when supplying the data information input to the first high-speed serial interface circuit to the RAM, the control circuit starts reproducing of the second frame synchronization signal in response to a switching instruction by the control information, and starts writing of the data information input to the second high-speed serial interface circuit into the RAM in synchronization with the second frame synchronization signal after writing of the data information for one frame in synchronization with the first frame synchronization signal is completed.
14. The data processor system according to claim 13 ,
wherein when supplying the data information input to the second high-speed serial interface circuit to the RAM, the control circuit starts writing of the data information input to the first high-speed serial interface circuit into the RAM in synchronization with the first frame synchronization signal after writing of the data information for one frame in synchronization with the second frame synchronization signal is completed in response to a switching instruction by the control information.