Bridge circuit to suppress echoes in communication devices
View Patent ↗Bridge circuit for echo suppression for a reception signal of a communication device connected to a transmission line, to which can be supplied a reception signal received via the transmission line and a transmission signal to be transmitted by the communication device via the transmission line. The bridge circuit is designed such that on balancing the bridge circuit, the reception signal there can be tapped echo-compensated with a transmission signal part generated by the transmission signal being suppressed. To balance the bridge circuit a variable simulation device is provided to simulate at least one circuit section of at least one bridge branch and connect with the at least one bridge branch. By such an arrangement, the signal level in the simulation device may be reduced so far that this can be designed as an integrated circuit and to be programmable.
1. An echo suppression device comprising:
a bridge circuit that includes a bridge branch having an impedance and a balancing circuit having another impedance higher than said impedance of said bridge branch, said balancing circuit connected in parallel to a portion of said bridge branch and being tunable to balance said bridge circuit;
said balancing circuit comprising an output to provide at least a portion of an echo-suppressed reception signal.
2. The balancing circuit of claim 1 , wherein said balancing circuit is an integrated circuit.
3. The balancing circuit of claim 1 , wherein said balancing circuit is connected in parallel to a portion of a further bridge branch of said bridge circuit.
4. The balancing circuit of claim 1 , wherein said impedance of said bridge branch comprises a first impedance, a second impedance and a third impedance connected in series, wherein said balancing circuit is connected in parallel to said second impedance.
5. A bridge circuit comprising:
at least a first bridge branch;
a second bridge branch; and,
a programmable impedance array connected in parallel with a portion of said second bridge branch.
6. The programmable impedance array of claim 5 , comprising an output to provide an output signal of said bridge circuit.
7. The programmable impedance array of claim 5 , wherein the programmable impedance array is integrated in an integrated circuit.
8. The programmable impedance array of claim 5 , wherein said programmable impedance array is programmable to balance the bridge circuit.
9. An echo suppression circuit comprising:
a bridge circuit, said bridge circuit including:
a bridge branch having a first node and a second node different from said first node;
a circuit portion connected with said bridge branch at said first node and at said second node, said circuit portion being configured to output an output voltage between a voltage at said first node and a voltage at said second node depending on an adjustment parameter.
10. The echo suppression circuit of claim 9 , wherein said bridge circuit further comprises a further bridge branch having a third node and a fourth node, said circuit portion being further connected with said further bridge branch at said third node and at said fourth node, said circuit portion being further configured to output a further output voltage between a voltage at said third node and a voltage at said fourth node depending on a further adjustment parameter.
11. The echo suppression circuit of claim 9 , wherein said circuit portion includes an impedance and said bridge branch includes another impedance between said first node and said second node, said impedance of said circuit portion being higher than said another impedance of said bridge branch.
12. The circuit portion of claim 9 , wherein said circuit portion comprises an integrated circuit.
13. The circuit portion of claim 9 , wherein said output voltage is at least part of an output signal of said bridge circuit.
14. The circuit portion of claim 9 , wherein said another impedance of said bridge branch comprises a first impedance, a second impedance and a third impedance connected in series, wherein said first node is located between said first impedance and said second impedance, and said second node is located between said second impedance and said third impedance.
15. A bridge circuit comprising:
a first bridge branch;
a second bridge branch; and,
a balancing circuit connected in parallel to a portion of said second bridge branch, said balancing circuit being tunable to balance said first bridge branch and said second bridge branch, said balancing circuit comprising an output to provide at least a portion of an output signal of said bridge circuit.
16. The bridge circuit of claim 15 , wherein said first bridge branch comprises an impedance of at least one element of the group comprising: a transmission line; a transmitter coupling said transmission line to said bridge circuit; and a communication device comprising the bridge circuit.
17. The bridge circuit of claim 15 , wherein said second bridge branch further comprises another impedance, said another impedance including:
a first impedance, a second impedance, and a third impedance;
a first node between said first impedance and said second impedance; and,
a second node between said second impedance and said third impedance;
wherein said balancing circuit is connected to said first node and to said second node.
18. The bridge circuit of claim 15 , wherein said output signal is configured to suppress an echo in a communication device.
19. The bridge circuit of claim 15 , wherein said balancing circuit comprises a programmable impedance array.
20. The bridge circuit of claim 15 , further comprising:
a third bridge branch;
a fourth bridge branch; and
said balancing circuit connected in parallel to a portion of said fourth bridge branch, said balancing circuit being tunable to balance said third bridge branch and said fourth bridge branch, said balancing circuit comprising a further output to provide a further portion of said output signal of said bridge circuit.
21. The bridge circuit of claim 15 , wherein said balancing circuit comprises an integrated circuit.
22. The bridge circuit of claim 17 , wherein said balancing circuit includes a balancing circuit impedance that is higher than said another impedance of said second bridge branch.
23. A method for balancing a bridge circuit comprising:
providing a first bridge branch;
providing a second bridge branch;
providing a balancing circuit connected in parallel to a portion of said second bridge branch;
tuning said balancing circuit to generate a balanced output signal; and,
tapping said balanced output signal at said balancing circuit.
24. The method of claim 23 , wherein said balancing circuit comprises a programmable impedance array, and wherein tuning said balancing circuit further comprises programming said programmable impedance array.