Method of fabricating back-illuminated imaging sensors
View Patent ↗A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. A substrate which includes an insulator layer and an epitaxial layer substantially overlying the insulator layer is provided. At least one bond pad region is formed extending into the epitaxial layer to a surface of the insulator layer. At least one bond pad is fabricated at least partially overlying the at least one bond pad region. At least one imaging component is fabricated at least partially overlying and extending into the epitaxial layer. A passivation layer is fabricated substantially overlying the epitaxial layer, the at least one bond pad, and the at least one imaging component. A handle wafer is bonded to the passivation layer. The at least a portion of the insulator layer and at least a portion of the bond pad region is etched to expose at least a portion of the at least one bond pad.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate comprising:
an insulator layer, and
an epitaxial layer substantially overlying the insulator layer,
forming at least one bond pad region extending into the epitaxial layer to a surface of the insulator layer;
fabricating at least one bond pad at least partially overlying the at least one bond pad region;
fabricating at least one component at least partially overlying and extending into the epitaxial layer;
fabricating a passivation layer substantially overlying the epitaxial layer, the at least one bond pad, and the at least one component;
bonding a handle wafer to the passivation layer, and
etching through at least a portion of the insulator layer and at least a portion of the bond pad region to expose at least a portion of the at least one bond pad.
2. The method for fabricating a semiconductor device according to claim 1 , further comprising forming a plurality of alignment keys substantially overlying the epitaxial layer.
3. The method for fabricating a semiconductor device according to claim 2 , wherein the step of forming a plurality of alignment keys substantially overlying the epitaxial layer further includes the steps of:
printing key patterns on a top portion of the epitaxial layer;
etching the underlying epitaxial layer below the key patterns using a trench etch process to etch away silicon and stopping on the underlying insulator layer; and
filling the opened Wenches with one of an oxide of silicon, silicon carbide, silicon nitride, and poly-silicon.
4. The method for fabricating a semiconductor device according to claim 1 , wherein the at least one bond pad region is formed at a location proximal to the alignment keys.
5. The method for fabricating a semiconductor device according to claim 1 , wherein the step of forming at least one bond pad region further includes the steps of:
creating an cutline of the at least one bond pad region substantially over the epitaxial layer using photolithography;
trench etching the epitaxial layer proximal to the outline to etch away silicon and stopping on the underlying insulator layer, thereby forming an open region; and
filling the open region with an oxide of silicon.
6. The method for fabricating a semiconductor device according to claim 2 , further comprising the step of bonding at least one optical component to the insulator layer using the plurality of alignment keys as guides.
7. The method for fabricating a semiconductor device according to claim 6 , wherein the at least one optical component includes at least one of color filters and micro-lenses.
8. The method for fabricating a semiconductor device according to claim 1 , wherein the step of fabricating at least one component at least partially overlying and extending into the epitaxial layer includes the step of fabricating at least one of CMOS imaging components, charge-coupled device (CCD) components, photodiodes, avalanche photodiodes, and phototransistors.
9. The method for fabricating a semiconductor device according to claim 1 , further comprising the step of bonding a handle wafer to the passivation layer.
10. The method for fabricating a semiconductor device according to claim 9 , wherein the step of bonding a handle wafer to the passivation layer further includes the step of polishing a top surface of the passivation layer using a chemical mechanical polishing process (CMP) to provide a flat surface for the addition of the handle wafer.
11. The method for fabricating a semiconductor device according to claim 10 , wherein the step of bonding the handle wafer to the passavation layer further includes the step of gluing the handle wafer to the flat surface.
12. The method for fabricating a semiconductor device according to claim 1 , wherein the step of etching at least a portion of the insulator layer and at least a portion of the bond pad region to expose at least a portion of the at least one bond pad further comprises the step of opening a second region in the at least one bond pad region using a trench oxide etch which stops on the passivation layer, the second region having a smaller volume than the at least one bond pad region, thereby forming sidewalls in the at least one bond pad region and exposing at least a portion of the bond pad.
13. The method for fabricating a semiconductor device according to claim 1 , further comprising the step of bonding a wire to the at least one bond pad.