Non-volatile memory embedded in a conventional logic process and methods for operating same
View Patent ↗A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.
1. A method comprising:
programming selected non-volatile memory cells in a selected row of an array of non-volatile memory cells arranged in one or more rows and columns, wherein each of the non-volatile memory cells includes an access transistor having source/drain regions of a first conductivity type and a capacitor structure having a diffusion region of a second conductivity type, opposite the first conductivity type, and a floating gate electrode common to the access transistor and the capacitor structure, and wherein the programming is implemented by band-to-band tunneling into the floating gate electrodes of the selected non-volatile memory cells; and
preventing programming of non-selected non-volatile memory cells in the selected row of the array, wherein the step of preventing programming is implemented by controlling a bias voltage applied to a source/drain region of the access transistor of each non-selected non-volatile memory cell in the selected row.
2. The method of claim 1 , further comprising: preventing programming of non-volatile memory cells in non-selected rows of the array by controlling a bias voltage applied to dedicated well regions associated with the non-selected rows, wherein the access transistors in each row are fabricated in a corresponding dedicated well region.
3. The method of claim 2 , wherein the step of preventing programming of non-volatile memory cells in the non-selected rows further comprising controlling a bias voltage applied to word lines associated with the non-selected rows, wherein the diffusion regions of the capacitor structures in each row are coupled to a corresponding word line.
4. The non-volatile memory system of claim 1 , further comprising implementing the band-to-band tunneling within each of the selected non-volatile memory cells by controlling a junction voltage between a source/drain region of each of the access transistors of the selected non-volatile memory cells and a well region in which each of the access transistors of the selected non-volatile memory cells is fabricated.
5. The method of claim 4 , further comprising biasing the junction voltage at about 5 Volts.
6. The method of claim 1 , further comprising simultaneously erasing all of the non-volatile memory cells in the array by inducing Fowler-Nordheim tunneling in all of the access transistors in the array.