IP Library Granted Patent US 8,156,496
Granted Patent B2
US 8,156,496 · App. 12/021,945 · Granted Apr 10, 2012

Data processing system and method

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Quick Facts
Patent No.
US 8,156,496
App. No.
12/021,945
Granted
Apr 10, 2012
Kind
B2
Abstract

A method of optimizing a thread in a system comprising a plurality of processors, the method comprising: determining performance of the thread on each of the processors; comparing the determined performances; and selecting a processor for executing the thread based on the comparison.

Claims (31)

1. A method of optimizing a thread in a system comprising a plurality of processors, the method comprising:

determining performance of the thread on each of the plurality of processors by:

executing the thread on a first processor for a first period;

measuring the performance of the thread on the first processor for a second period; and

repeating executing and measuring of the performance of the thread on each of the remaining processors for subsequent periods;

comparing the determined performances; and

selecting one of the plurality of processors for executing the thread based on the comparison.

2. A method as claimed in claim 1 , wherein determining the performance of the thread on each of the plurality of processors comprises measuring a cycles per instruction (CPI) value of the thread on each of the plurality of processors.

3. A method as claimed in claim 1 , wherein selecting one of the plurality of processors comprises selecting the processor with the highest determined performance.

4. A method as claimed in claim 1 , comprising binding the thread to the selected processor for a subsequent execution of the thread.

5. A non-transitory computer readable storage medium having loaded thereon a computer program for optimizing a thread on a system comprising a plurality of processors, the computer program comprising computer readable code to:

determine performance of the thread on each of the plurality of processors through:

execution of the thread on a first processor for a first period;

measurement of the performance of the thread on the first processor for a second period; and

repetition of execution and measurement of the performance of the thread on each of the remaining processors for subsequent periods;

compare the determined performances; and

select one of the plurality of processors for executing the thread based on the comparison.

6. A non-transitory computer readable storage medium as claimed in claim 5 , wherein the computer readable code to determine the performance of the thread on each of the plurality of processors comprises computer readable code to measure a cycles per instruction (CPI) value of the thread on each of the plurality of processors.

7. A non-transitory computer readable storage medium as claimed in claim 5 , wherein the computer readable code to select one of the plurality of processors comprises computer readable code to select the processor with the highest determined performance.

8. A non-transitory computer readable storage medium as claimed in claim 5 , further comprising computer readable code to bind the thread to the selected processor for a subsequent execution of the thread.

9. An apparatus comprising:

a plurality of processors; and

a data storage device on which is stored computer readable code to:

determine performance of the thread on each of the plurality of processors through:

execution of the thread on a first processor for a first period;

measurement of the performance of the thread on the first processor for a second period; and

repetition of execution and measurement of the performance of the thread on each of the remaining processors for subsequent periods;

compare the determined performances; and

select one of the plurality of processors of the plurality of processor to execute the thread based on the comparison.

10. The apparatus according to claim 9 , wherein the computer readable code to determine the performance of the thread on each of the plurality of processors comprises computer readable code to measure a cycles per instruction (CPI) value of the thread on each of the plurality of processors, and wherein the computer readable code to select the processor comprises computer readable code to select the processor with the highest determined performance.

11. The apparatus according to claim 9 , further comprising computer readable code to bind the thread to the selected processor for a subsequent execution of the thread.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2021
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 057650/0537 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2008
From: NAGARAJAN, PADMANABHAN SELVAKUMARAPALAYAM; SHANKAR, GANESH HANDIGE
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 020445/0408 →