Apparatus and method for isolating portions of a scan path of a system-on-chip

1. A system-on-chip apparatus, the apparatus comprising:

a scan path comprising a first layer having a plurality of components, and a second layer having at least one component, wherein the second layer is adapted for being dynamically selected and deselected;

wherein propagation of data within the first layer is controlled using at least one control signal;

wherein propagation of data within the second layer is controlled using the at least one control signal and a layer selection control signal from the first layer, wherein the layer selection control signal is adapted for controlling propagation of data within the second layer independent of propagation of data within the first layer.

2. The apparatus of claim 1 , wherein each of the components of the first layer include a hierarchy-enabling component adapted for selecting and deselecting the second layer, wherein the at least one component of the second layer includes at least one non-hierarchy-enabling component.

3. The apparatus of claim 2 , wherein each of the at least one hierarchy-enabling component is adapted for generating a layer selection control signal adapted for selecting and deselecting the second layer.

4. The apparatus of claim 3 , further comprising a control logic adapted for using a layer selection control signal from the hierarchy-enabling component to filter application of the at least one control signal to the at least one non-hierarchy-enabling component of the second layer.

5. The apparatus of claim 4 , wherein the layer selection control signal comprises a first control signal and a second control signal.

6. The apparatus of claim 5 , wherein the at least one non-hierarchy-enabling component of the second layer comprises a first register and a second register.

7. The apparatus of claim 6 , wherein the control logic comprises a first portion for controlling the first register of the at least one non-hierarchy-enabling component and a second portion for controlling the second register of the at least one non-hierarchy-enabling component.

8. The apparatus of claim 7 , wherein the first portion of the control logic comprises a first AND gate, wherein a first input to the first AND gate is the first control signal and a second input to the first AND gate is the hierarchy selection control signal.

9. The apparatus of claim 8 , wherein an output of the first AND gate is coupled to the at least one non-hierarchy-enabling component of the second layer as a first shift control signal adapted for controlling shifting of data into the first register.

10. The apparatus of claim 9 , wherein the second portion of the control logic comprises a second AND gate, wherein a first input to the second AND gate is the second control signal and a second input to the second AND gate is the layer selection control signal.

11. The apparatus of claim 10 , wherein an output of the second AND gate is coupled to the at least one non-hierarchy-enabling component of the second layer as a second shift control signal adapted for controlling shifting of data into the second register.

12. A system-on-chip apparatus, the apparatus comprising:

a scan path comprising a plurality of segments communicatively coupled to one or more input and output (I/O) ports of the system-on-chip, a derivation-enabling cell coupled to one or more segments wherein said derivation-enabling cell is disposed between two segments and a third segment of the plurality of segments to thereby form a multi-level derivation; and

control logic for enabling access to one or more cores with a single scan operation that controls configuration of the entire scan path, the one or more cores being coupled to the plurality of segments.

13. The system of claim 12 , wherein each of the plurality of segments further comprises a single layer on a level as well as one or more hierarchical or subordinate levels.

14. The apparatus of claim 13 , wherein a first hierarchical level comprises a plurality of components and a second hierarchical level comprises at least one component, wherein data is propagated within the first hierarchical level using at least one control signal applied to the components of the first hierarchical level.

15. The apparatus of claim 14 , wherein the at least one component of the second hierarchical level includes at least one non-hierarchy-enabling component.

16. The apparatus of claim 15 , wherein the control logic is adapted for using a hierarchy selection control signal from the hierarchy-enabling component to filter application of the at least one control signal to the at least one non-hierarchy-enabling component of the second hierarchical level.

17. The apparatus of claim 15 , wherein the at least one non-hierarchy-enabling component of the second hierarchical level is coupled to an instrument, wherein the control logic prevents data from being propagated within the second hierarchical level when the second hierarchical level is deselected to enable thereby parallel testing of the instrument while data continues to be propagated through the first hierarchical level.

18. The apparatus of claim 17 , wherein the instrument is adapted to provide a testing result to at least one of the at least one non-hierarchy-enabling component of the second hierarchical level.

19. The apparatus of claim 13 , wherein, when the second hierarchical level is deselected, the control logic prevents data from being propagated within the second hierarchical level while data is propagated within the first hierarchical level.

20. The apparatus of claim 13 , wherein, when the second hierarchical level is selected, the control logic allows data to be propagated within the second hierarchical level while data is propagated within the first hierarchical level.

21. The apparatus of claim 13 , wherein the components of the first hierarchical level include a hierarchy-enabling component adapted for selecting and deselecting the second hierarchical level.