Apparatus and method for controlling dynamic modification of a scan path
View Patent ↗The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.
1. A system-on-chip apparatus, comprising:
a testing scan path comprising a plurality of testing components including at least one hierarchy-enabling testing component communicatively coupled to the at least one hierarchy-enabling testing component of the testing scan path; and
a control scan path comprising at least one control component, the at least one control component is adapted to control the at least one hierarchy-enabling testing component in a manner for dynamically modifying the testing scan path;
wherein the testing scan path and the control scan path are independent.
2. The apparatus of claim 1 , wherein the testing scan path includes a hierarchy having a first hierarchical level and a second hierarchical level, wherein dynamically modifying the testing scan path comprises dynamically modifying the hierarchy of the testing scan path.
3. The apparatus of claim 2 , wherein dynamically modifying the hierarchy of the testing scan path comprises one of selecting the second hierarchical level to activate the second hierarchical level and deselecting the second hierarchical level to deactivate the second hierarchical level.
4. The apparatus of claim 1 , wherein the testing scan path is adapted for propagating a testing bitstream, wherein the control scan path is adapted for propagating a control bitstream.
5. The apparatus of claim 4 , wherein the control bitstream is adapted for use by the at least one control component to control the at least one hierarchy-enabling testing component in a manner for modifying the testing scan path.
6. The apparatus of claim 1 , wherein the control component is adapted to provide a control signal for controlling a logic element of the hierarchy-enabling testing component.
7. A system-on-chip apparatus, comprising:
a testing scan path comprising a plurality of non-hierarchy-enabling testing components and at least one hierarchy-enabling component communicatively coupled to the at least one hierarchy-enabling testing component of the testing scan path; and
a control scan path comprising the at least one hierarchy-enabling component;
wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path.
8. The apparatus of claim 7 , wherein the testing scan path includes a hierarchy having a first hierarchical level and a second hierarchical level, wherein dynamically modifying the testing scan path comprises dynamically modifying the hierarchy of the testing scan path.
9. The apparatus of claim 7 , wherein the testing scan path is adapted for propagating a testing bitstream and the control scan path is adapted for propagating a control bitstream.
10. The apparatus of claim 9 , wherein the control bitstream controls at least a portion of hierarchy-enabling component in a manner for dynamically modifying the testing scan path.
11. The apparatus of claim 7 , wherein each of the at least one hierarchy-enabling component comprises a select element adapted for selecting between a testing bitstream and a control bitstream.
12. The apparatus of claim 7 , wherein the testing scan path and control scan path are independent.
13. A system-on-chip apparatus, comprising:
a testing scan path communicatively coupled to a control scan path, the testing scan path is adapted for propagating a testing bitstream; and
the control scan path is adapted for propagating a control bitstream;
wherein the control bitstream is adapted for modifying propagation of the testing bitstream within the testing scan path.
14. The apparatus of claim 13 , wherein the testing scan path comprises a plurality of non-hierarchy-enabling testing components and at least one hierarchy-enabling testing component.
15. The apparatus of claim 14 , wherein the control scan path comprises at least one control component.
16. The apparatus of claim 15 , wherein the at least one control component is coupled to the at least one hierarchy-enabling testing component in a manner for modifying propagation of the testing bitstream within the testing scan path.
17. The apparatus of claim 13 , wherein the testing scan path is formed using a plurality of non-hierarchy-enabling testing components and at least one hierarchy-enabling component.
18. The apparatus of claim 13 , wherein the control scan path is formed using the at least one hierarchy-enabling component.
19. The apparatus of claim 18 , wherein the at least one hierarchy-enabling component is adapted for using the control bitstream of the control scan path to modify propagation of the testing bitstream within the testing scan path.
20. The apparatus of claim 13 , wherein the testing scan path comprises a first hierarchical level and a second hierarchical level, wherein the second hierarchical level is adapted for being dynamically selected to be activated and dynamically deselected to be deactivated.