Frequency synthesis using upconversion PLL processes

1. A circuit, comprising:

a frequency-locked loop portion configured to receive an input frequency and to generate an upconverted intermediate frequency and a frequency information indicative of a needed frequency correction of a frequency-locked loop output frequency;

an intermediate portion configured to receive the upconverted intermediate frequency and a reference frequency, and further configured to provide an intermediate output that is either the upconverted intermediate frequency or the reference frequency; and

a phase-locked loop portion configured to receive the intermediate output and to generate a phase-locked output frequency based on the frequency information.

2. The circuit of claim 1 , wherein the frequency-locked loop portion includes a digitally-controlled oscillator configured to generate the upconverted intermediate frequency.

3. The circuit of claim 2 , wherein the frequency-locked loop portion includes a digital control coupled to the digitally-controlled oscillator to provide a control signal to the digitally-controlled oscillator based on a frequency measurement derived out of the input frequency.

4. The circuit of claim 1 , wherein the phase-locked loop portion includes an analog phase-locked loop having:

a phase comparator configured to receive the intermediate output and a phase adjustment signal; and

a multi-modulus divider coupled to the phase comparator and configured to provide the phase adjustment signal based at least partially on the frequency information.

5. The circuit of claim 4 , further comprising a sigma delta modulator coupled to receive the frequency information and to provide a control signal to the multi-modulus divider based at least partially on the frequency information.

6. The circuit of claim 5 , wherein the phase comparator includes a phase detector coupled to receive the phase adjustment signal, and a charge pump coupled to generate a charging current, and wherein the analog phase-locked loop further includes:

a loop filter coupled to receive the charging current and to output a smoothed voltage; and

a voltage controlled oscillator configured to receive the smoothed voltage and to provide the phase-locked output frequency.

7. The circuit of claim 1 , wherein the phase-locked loop portion includes a digital phase-locked loop.

8. The circuit of claim 7 , further comprising a first frequency measurement component of the frequency-locked loop portion configured to provide the frequency information to the digital phase-locked loop and a second frequency measurement component configured to provide a measurement of the phase-locked output frequency to the digital phase-locked loop.

9. The circuit of claim 1 , wherein the intermediate portion includes a multiplexer.

10. An electronic device, comprising:

a processor; and

a communication component operatively coupled to the processor and configured to at least one of receive and transmit communication signals, the communication component including a frequency synthesizer component having:

a frequency-locked loop portion configured to receive an input frequency and to generate an upconverted intermediate frequency and a frequency information indicative of a frequency correction;

an intermediate portion coupled to the frequency-locked loop portion and configured to receive the upconverted intermediate frequency and a reference frequency, and further configured to provide an intermediate output that is either the upconverted intermediate frequency or the reference frequency; and

a phase-locked loop portion coupled to the intermediate portion and configured to receive the intermediate output and to generate a phase-locked output frequency based on the frequency information.

11. The device of claim 10 , wherein the frequency-locked loop portion includes a digitally-controlled oscillator configured to generate the upconverted intermediate frequency, and wherein the phase-locked loop portion includes a voltage controlled oscillator configured to provide the phase-locked output frequency.

12. The device of claim 11 , wherein the frequency-locked loop portion includes a digital control coupled to provide a control signal to the digitally-controlled oscillator based on a frequency measurement of the input frequency.

13. The device of claim 11 , further comprising a sigma delta modulator coupled to receive the frequency information and to provide a control signal to the phase-locked loop based at least partially on the frequency information.

14. The device of claim 10 , wherein the frequency-locked loop portion is further configured to deactivate generation of the upconverted intermediate frequency when reference frequency is adequate and the intermediate portion outputs the reference frequency.

15. A method, comprising:

receiving a low frequency input;

providing an upconverted intermediate signal;

providing a frequency information indicative of a frequency correction;

selecting one of the upconverted intermediate signal and a high frequency reference; and

frequency-locking the selected upconverted intermediate signal or the high frequency reference based on the frequency information to provide an upconverted phase-locked output.

16. The method of claim 15 , wherein providing an upconverted intermediate signal includes controlling an oscillator to generate the upconverted intermediate signal based on a frequency measurement of the low frequency input.

17. The method of claim 16 , wherein the oscillator generates an oscillator output, the method further comprising dividing down the oscillator output to generate the upconverted intermediate signal.

18. The method of claim 15 , wherein frequency locking the selected upconverted intermediate signal or the high frequency reference includes:

receiving the frequency information into a control component; and

adjusting a phase-locked loop using a control signal from the control component.

19. The method of claim 18 , wherein adjusting the phase-locked loop includes adjusting a digital phase-locked loop.

20. The device of claim 8 , wherein the second frequency measurement component is configured to provide the measurement of the phase-locked output frequency to a digital control of the frequency-locked loop portion.